• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.40-45
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• 1994

$112^{\circ}$ rot. x-cut $LiTaO_{3}$ wafer was used as the substrate of SAW gas sensor. Dual delay line SAW device with IDTs which consist of the reference delay line and the sensing delay line was fabricated using photolithigraphy. Each IDTs had 10 finger pairs and finger spacing is 10 microns. One delay line channel is the reference, while the second is the sensing channel with Pb-phthalocyanine film in the propagation path. Pb-phthalocyanine film which is p-type organic semiconductor was evaporated in $10^{-5}$ torr vacuum using shadow mask selectively. Dual delay line oscillator was constructed by using the rf amplifier and AGC. Frequency of the IDTs had the range of $87{\sim}$89 MHz oscillation frequency. Oscillation frequency shifts were investigated as a function of the temperature and the concentration of $NO_{2}$ gas.

• Journal of electromagnetic engineering and science
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• v.12 no.2
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• pp.166-170
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• 2012

This paper presents a tunable composite right/left-handed (CRLH) delay line for a delay line discriminator that linearizes modulated frequency sweep in a frequency modulated continuous wave (FMCW) radar transmitter. The tunable delay line consists of 8 cascaded unit cells with series varactor diodes and shunt inductors. The reverse bias voltage of the varactor diode controlled the group delay through its junction capacitance. The measured results demonstrate a group delay of 8.12 ns and an insertion loss of 4.5 dB at 250 MHz, while a control voltage can be used to adjust the group delay by approximately 15 ns. A group delay per unit cell of approximately 1 ns was obtained, which is very large when compared with previously published results. This group delay can be used effectively in FMCW radar transmitters.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• Korean Journal of Optics and Photonics
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• v.18 no.4
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• pp.274-279
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• 2007

We fabricated and characterized an optical delay line for optical coherence tomography (OCT). The delay line was composed of a cylindrical piezoelectric transduce (PZT) and a single mode optical fiber. The OCT system used a duplex scanning optical delay line which was symmetrically driven in the reference and sample arms. We showed that the sinusoidal-wave was superior to a triangular-wave for driving the optical delay line for scanning depth and repeatability.

• Journal of the Optical Society of Korea
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• v.7 no.4
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• pp.224-229
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• 2003

We report a novel optical delay line that can be implemented using only optical fiber and fiber devices without the need for any bulk-optic devices such as lens, prism, and moving mirror. The dispersive property of a chirped fiber Bragg grating (CFBG) is exploited to get the delay. The proposed delay line constitutes two identical CFBGs cascaded in the reverse order with one of them being strained. Analysis reveals that the small displacement or the strain applied on the CFBG is effectively amplified in the delay line by the ratio of the minimum resonant wavelength and the reflection bandwidth of the CFBG. The dispersion properties of the CFBG with and without the strain are analyzed in detail. The theoretical performance of the proposed delay line is also discussed. Applications of the proposed delay line are expected in the field of high-speed optical coherence tomograpy.

• Journal of Astronomy and Space Sciences
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• v.19 no.1
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• pp.57-66
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• 2002

We designed two-dimensional position sensitive MCP(mixt.ochannel plate) detector for FIMS, which is composed of MCP, delay line anode, and delay line readout elec-tronics. And also, we fabricated and tested for the operation stability and resolution of the delay line readout electronic system. An anode simulator and a stimulator were used instead of the real MCP and anode during the test to see the electronic contribution to the resolution. The readout electronics was operated stably and showed time resolution of about 560 ps for the spectral direction and about 100 ps for the image direction respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.33-40
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• 1992

The design method of signal delay line system using indirect frequency synthesizer is presented. The variable signal delay line system with 2[nsec] step of delay time at center frequency 60[MHz], bandwidth 500[KHz] and range 5.24-5.81[x10S0-6Tsec] is designed and fabricated. The results were met with good characteristics to be variable delay time of average 2.01[nsec] per step.

• Journal of Korean Society of Transportation
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• v.10 no.1
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• pp.41-54
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• 1992

The purpose of this thesis is to construct a model to estimate the delay that vehicles arriving randomly will be experienced at an isolated singalized intersection. To do this the following objectives are set in this study: (i) An what distance a random arrival pattern occurs after a platoon of vehicles are dis-charged from the stop line; (ii) A model which estimates the average delay per through-vehicle with respect to the de-gree of saturation; and (iii) The relation between the stepped delay and average approach delay per vehicle. The following are the findings of this study: (i) A random arrival pattern on the first second and third lanes occur 300,400 and 300m downstream from stop line rdspectively. A random arrival pattern on lane group occurs 500m downstream from the stop line ; (ii) A model for the estimation of approach delay has been developed in such a way that up to x=0.7 the delay increases linearly and beyond 0.7 the delay increases rapidly in a form of second order polynomial due to high degree of saturation : and (iii) Approach delay equals approximately 1.21 times of stopped delay.

• Journal of IKEEE
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• v.20 no.2
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• pp.167-170
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• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.394-397
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• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.