• Title/Summary/Keyword: Deep Trench

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Realization of High Q Inductor on Low Resistivity Silicon Wafer using a New and simple Trench Technique (새로운 트랜치 방법을 이용한 저저항 실리콘 기판에서의 High Q 인덕터의 구현)

  • 이홍수;이진효유현규김대용
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.629-632
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    • 1998
  • This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

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Alumina masking for deep trench of InGaN/GaN blue LED in ICP dry etching process

  • 백하봉;권용희;이인구;이은철;김근주
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2005.09a
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    • pp.59-62
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    • 2005
  • 백색 LED 램프를 제조하는 공정에서 램프간의 전기적 개방상태의 절연상태를 유지하기 위해 사파이어 기판 위에 성장된 GaN 계 반도체 에피박막층을 제거하기 위해 유도 결합형 플라즈마 식각 공정을 이용하였다. 4 미크론의 두께를 갖는 GaN 층을 식각하는데 있어 식각 방지 마스킹 물질로 포토레지스트, $SiO_2,\;Si_{3}N_4$$Al_{2}O_3$를 시험하였다. 동일한 전력 및 가스유량상태에서 $Al_{2}O_3$만 에피층을 보호할 수 있음을 확인하였다.

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Analysis on the concept design of the nuclear waste disposal site in foreign country (해외 방사성 폐기물 처분장 개념 설계 분석)

  • Seo, Kyoung-Won;Kim, Woong-Ku;Baek, Ki-Hyun;Jun, Seong-Keun
    • Proceedings of the Korean Geotechical Society Conference
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    • 2010.03a
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    • pp.791-800
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    • 2010
  • This paper presents the construction status and the conceptual designs of midium and high level radioactive waste disposal facilities from all around world. For the midium radioactive waste, a shallow disposal using trench or a deep depth disposal are adopted. However, these are rather focusing on the social and cultural point of view than the technical. Meanwhile, the high level radioactive waste is basically disposed in the deep underground. The corresponding ground conditions are usually dense and composed of sedimentary and crystalline rocks mainly with low permeability. A barrier system is made of canister which consists of copper, titanium, and tin. The inner and outer side of the canister are composed of different materials respectively.

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A Study on sub 0.1$\mu\textrm{m}$ ULSI Device Quality Using Novel Titanium Silicide Formation Process & STI (새로운 티타늅 실리사이드 형성공정과 STI를 이용한 서브 0,1$\mu\textrm{m}$ ULSI급 소자의 특성연구)

  • Eom, Geum-Yong;O, Hwan-Sul
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.1-7
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    • 2002
  • Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

A Study on the Electrical Characteristics of Ultra Thin Gate Oxide

  • Eom, Gum-Yong
    • Transactions on Electrical and Electronic Materials
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    • v.5 no.5
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    • pp.169-172
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    • 2004
  • Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ~ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

Diversity of Deep-sea Piezophiles and Their Molecular Adaptations to High-pressure Environment

  • Kato, Chiaki;Sato, Takako;Tamegai, Hideyuki;Nakasone, Kaoru
    • Proceedings of the Microbiological Society of Korea Conference
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    • 2007.05a
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    • pp.80-82
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    • 2007
  • We have isolated numerous cold deep-sea adapted microorganisms (piezophilic, formerly referred to as "barophilic" bacteria) using deep-sea research submersibles. Many of the isolates are novel psychrophilic bacteria, and we have identified several new piezophilic species, i.e., Photobacterium profundum, Shewanella violacea, Moritella japonica, Moritella yayanosii, Psychromonas kaikoi, and Colwellia piezophila. These piezophiles are involving to five genera in gamma-Proteobacteria subgroup and produce significant amounts of unsaturated fatty acids in their cell membrane fractions to maintain the membrane fluidity in cold and high-pressure environments. Piezophilic microorganisms have been identified in many deep-sea bottoms of many of the world oceans. Therefore, these microbes are well distributed on our planet. One of the isolated deep-sea piezophiles, Shewanella violacea strain DSS12 is a psychrophilic, moderately piezophilic bacterium from a sediment sample collected at the Ryukyu Trench (depth: 5,110 m), which grows optimally at 30 MPa and $8^{\circ}C$ but also grows at atmospheric pressure (0.1 MPa) and $8^{\circ}C$. We have examined this strain to elucidate the molecular basis for gene regulation at different pressure conditions because this strain is useful as a model bacterium for comparing the various features of bacterial physiology under pressure conditions. In addition, we completed the sequencing of the entire genome of this piezophilic bacterium and we expect that many biotechnologically useful genes will be identified from the genome information.

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Depth-dependent Variations in Elemental and Mineral Distribution in the Deep Oceanic Floor Sediments (WP21GPC04) near the Mariana Trench in the Western Pacific Ocean (마리아나 해구에 인접한 서태평양 심해평원의 정점 WP21GPC04에서 수집된 해양 퇴적물의 깊이에 따른 원소 및 광물 분포 변화)

  • Junte Heo;Seohee Yun;Jonguk Kim;Young Tak Ko;Yongjae Lee
    • Economic and Environmental Geology
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    • v.56 no.5
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    • pp.581-588
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    • 2023
  • This study reports depth-dependent elemental distribution and mineral abundance of the oceanic sediment sample (WP21GPC04) near the Mariana Trench collected during the WP21 expedition in 2021. The elemental distribution determined by μ-XRF shows no significant differences with varying depth, with an average SiO2 53.91 wt%, FeO 4.48 wt%, Al2O3 16.56 wt%, MgO 2.56 wt%, CaO 4.79 wt%, Na2O 3.52 wt%, K2O 5.48 wt%, similar to the average chemical composition of global subducting sediments (GLOSS). The mineral abundances analyzed using synchrotron XRD, however, vary with depth. While quartz, mica, and plagioclase were identified at all depths, chlorite was found at shallow depths, and zeolite group minerals, phillipsite and heulandite, showed a gradual change in phase fraction with depth. This suggests a change in sedimentation and alteration environments in the region, or the potential for coexistence emerges due to similar sediment stability. Overall, this study will provide a basis for the future investigations on the evolution of sedimentary environment near the Mariana Trench in the western Pacific Ocean and the phase distribution and the behavior of subducting oceanic sediments, which will affect the lithological and geochemical characteristics of the Mariana susduction system.

A Study on the Reflow Characteristics of Cu Thin Film (구리 박막의 Reflow 특성에 관한 연구)

  • Kim, Dong-Won;Gwon, In-Ho
    • Korean Journal of Materials Research
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    • v.9 no.2
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    • pp.124-131
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    • 1999
  • Copper film, which is expected to be used as interconnection material for 1 giga DRAM integrated circuits was deposited on hole and trench patterns by Metal Organic Chemical Vapor Deposition(MOCVD) method. After a reflow process, contact and L/S patterns were filled by copper and the characteristics of the Cu reflow process were investigated. When deposited Cu films were reflowed, grain growth and agglomeration of Cu have occurred in surfaces and inner parts of patterns as well as complete filling in patterns. Also Cu thin oxide layers were formed on the surface of Cu films reflowed in $O_2$ambient. Agglomeration and oxidation of Cu had bad influence on the electrical properties of Cu films especially, therefore, their removal and prevention were studied simultaneously. As a pattern size is decreased, preferential reflow takes place inside the patterns and this makes advantages in filling patterns of deep submicron size completely. With Cu reflow process, we could fill the patterns with the size of deep sub-micron and it is expected that Cu reflow process could meet the conditions of excellent interconnection for 1 giga DRAM device when it is combined with Cu MOCVD and CMP process.

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Fabrication of Nano-bridge Using a Suspended Multi-Wall Carbon Nanotube (다중벽 탄소나노튜브를 이용한 나노 브리지 제작)

  • Lee, Jong-Hong;Won, Moon-Cheol;Seo, Hee-Won;Song, Jin-Woo;Han, Chang-Soo
    • Journal of the Korean Society for Precision Engineering
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    • v.24 no.3 s.192
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    • pp.134-139
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    • 2007
  • We report the suspension of individual multi-walled carbon nanotubes (MWNTs) from the bottom substrate using deep trench electrodes that were fabricated using optical lithography. During drying of the solution in dielectrophoretic assembly, the capillary force pulls the MWNT toward the bottom substrate, and it then remains as a deformed structure adhering to the bottom substrate after the solution has dried out. Small-diameter MWNTs cannot be suspended using thin electrodes with large gaps, but large-diameter MWNTs can be suspended using thicker electrodes. We present the statistical experimental results for successful suspension, as well as the feasible conditions for a MWNT suspension based on a theoretical approach.

Planarization characteristics as a function of polishing time of STI-CMP process (STI CMP 공정의 연마시간에 따른 평탄화 특성)

  • 김철복;서용진;김상용;이우선;장의구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.33-36
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    • 2001
  • Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

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