• Title/Summary/Keyword: Deep Depletion MOSFET

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3-Dimensional Numerical Analysis of Deep Depletion Buried Channel MOSFETs and CCDs

  • Kim Man-Ho
    • Journal of Electrical Engineering and Technology
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    • v.1 no.3
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    • pp.396-405
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    • 2006
  • The visual analysis of buried channel (Be) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of 'EVEREST' for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately $4{\sim}5%$ error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

Lateral Channel Doping Profile Measurements Using Extraction Data of Drain Voltage-Dependent Gate-Bulk MOSFET Capacitance (드레인 전압 종속 게이트-벌크 MOSFET 캐패시턴스 추출 데이터를 사용한 측면 채널 도핑 분포 측정)

  • Choi, Min-Kwon;Kim, Ju-Young;Lee, Seong-Hearn
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.10
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    • pp.62-66
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    • 2011
  • In this study, a new RF method to extract the drain-source voltage Vds-dependent gate-bulk capacitance of deep-submicron MOSFETs is developed by determining Vds-independent gate-source overlap capacitance using measured S-parameters. The accuracy of extraction method is verified by observing good agreements between the measured and modeled S-parameters. The lateral channel doping profile in the drain region is experimentally measured using a Vds-dependent curve of the overlap and depletion length obtained from the extracted data.

The Characterizing Analysis of a Buried-Channel MOSFET based on the 3-D Numerical Simulation

  • Kim, Man-Ho;Kim, Jong-Soo
    • Journal of Electrical Engineering and Technology
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    • v.2 no.2
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    • pp.267-273
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    • 2007
  • A depletion-mode MOSFET has been analyzed to evaluate its electrical behavior using a novel 3-D numerical simulation package. The characterizing analysis of the BC MOSFET was performed through short-channel narrow-channel and small-geometry effects that are investigated, in detail, in terms of the threshold voltage. The DIBL effect becomes significant for a short-channel device with a channel length of $<\;3({\mu}m)$. For narrow-channel devices the variation of the threshold voltage was sharp for $<4({\mu}m)$ due to the strong narrow-channel effect. In the case of small-geometry devices, the shift of the threshold voltage was less sensitive due to the combination of the DIBL and substrate bias effects, as compared with that observed from the short-channel and narrow-channel devices. The characterizing analysis of the narrow-channel and small-geometry devices, especially with channel width of $<\;4({\mu}m)$ and channel area of $<\;4{\times}4({\mu}m^2)$ respectively, can be accurately performed only from a 3-D numerical simulation due to their sharp variations in threshold voltages.