• ETRI Journal
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• v.29 no.3
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• pp.363-370
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• 2007

In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half-rate turbo decoder designed for binary quadrature phase-shift keying (B/QPSK) modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implement the proposed scheme on a field-programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.3 s.345
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• pp.95-102
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• 2006

This paper proposes the KB-Fano algorithm which has lower decoding complexity by applying modified Fano-like metric bias to the conventional K-best algorithm. Additionally, an efficient K-best decoding algorithm, named the KR-Fano scheme, is proposed by jointly combining the K-reduction and the KB-Fano schemes. Simulations show that the proposed algerian provides the remarkable improvement from the viewpoints of the BER performance and the decoding complexity as compared to the conventional K-best scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.442-449
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• 2005

In this paper, we introduce three kinds of simplified high-speed decoding algorithms for turbo product decoder. First, A parallel decoder structure, the row and column decoders operate in parallel, is proposed. Second, HAD(Hard Decision Aided) algorithm is used for early-stopping algorithm. Lastly, P-Parallel TPC decoder is a parallel decoding scheme, processing P rows and P columns in parallel instead of decoding one by one as that in the original scheme.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.174-183
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• 2011

This paper is about a bar code decoding algorithm developed for smart phone applications. The algorithm consists of bar code data extraction procedure, bar code signal estimation procedure, and bar code decoding procedure. To detect the peak bar code module, a DSTW had been applied because of its outstanding performance in ECG peak detection. In order to minimize errors due to non-uniform light effect, the proposed algorithm was acted as a baseline wandering filter based on module peaks detection. The algorithm had been tested to evaluate the performance under the conditions of blurring, non-uniformed light and white noises. The algorithm had shown excellent performance in reconstruction of bar code decoding, compared to other conventional methods. In order to show the possibility of applying the algorithm to a smart phone, a real UPC-A type 150 bar code pictures obtained from a smart phone camera was applied to the algorithm, achieving the correct recognition rate of 97.33%.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.257-265
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• 2000

Turbo Code decoder is an iterate decoding technology, which extracts extrinsic information from the bit to be decoded by calculating both forward and backward metrics in each decoding step, and uses the information to the next decoding step. Viterbi decoder, which is for a convolutional code, runs continuous mode, while Turbo Code decoder runs by block unit. There are algorithms used in a decoder : which are MAP(maximum a posteriori) algorithm requiring very complicated calculation and SOVA(soft output Viterbi algorithm) using Viterbi algorithm suggested by Hagenauer, and it is known that the decoding performance of MAP is better. The result of this make experimentation shows that the performance of SOVA, which has half complex algorithm compare to MAP, is almost same as the performance of MAP when the SOVA decoding performance is supplemented with Robust equalization techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.148-154
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard are required a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method is reduced number of unnecessary iteration. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7C
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• pp.618-627
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• 2010

In this paper, we propose an adaptive K-best algorithm in which the number K of candidates is changed according to the differences of level radii. We also compare the bit error performance and complexity of the proposed algorithm with those of several conventional K-best algorithms, where the complexity is defined as the total number of candidates of which partial Euclidean distances have to be calculated. The proposed algorithm adaptively decides K at each level by eliminating the symbols, whose differences of radii are larger than a threshold, from the set of candidates, and the maximum or average value of differences can be adopted as the threshold. The proposed decoding algorithm shows the better bit error performance and the lower complexity than a conventional K-best decoding algorithm with a constant K, and also has a similar bit error performance and the lower complexity than other adaptive K-best algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.97-103
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• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1419-1426
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• 1997

A new SCEE(Syndrome Check Error Estimation) decoding method for convolutional code and concatenated SCEE/RS (Reed-Solomon) conding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are drived when some combination of predecoder-reencoder is used. Computer simulation results show that the compuatational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi-decoder without degratation of the $P_{e}$ performance. Also, the concatenated SCEE/RS decoder has almost the same complexity of a RS decoder and its coding gain is higher than that of soft decision Viterbi or RS decoder respectively.