• Journal of Korea Multimedia Society
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• v.19 no.2
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• pp.200-208
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• 2016

Compressed sensing is a signal processing technique for efficiently acquiring and reconstructing in an under-sampled (i.e., under Nyquist rate) representation. A block compressed sensing with projected Landweber (BCS-SPL) framework is most widely known, but, it has high computational complexity at decoder side. In this paper, by introducing adaptive exit criteria instead of fixed exit criteria to SPL framework, an effective fast algorithm is designed in such a way that it can utilize efficiently the sparsity property in DCT coefficients during the iterative thresholding process. Experimental results show that the proposed algorithm results in the significant reduction of the decoding time, while providing better visual qualities than conventional algorithm.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.611-614
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• 2002

In this paper, a novel error concealment, algorithm is proposed for the MPEG-4 video decoding. Apart from existing algorithms which fail to exhibit stable performance over various video sequences and error patterns, the proposed algorithm adopts a new hybrid scheme, which can achieve a consistent performance with reduced computational complexity. This algorithm is implemented on the basis of the MPEG-4 decoder, and the experimental results demonstrate that the new approach provides acceptable performance both subjectively and objectively at various bit error rates and video sequences.

• Journal of Advanced Marine Engineering and Technology
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• v.25 no.2
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• pp.375-382
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• 2001

In this study, an adapted Turbo Coding Algorithm for reducing communication error of a fire detection system for marine vessels, especially image transmission via power lone. Because it is necessary that this system communicate larger and faster than previous method, this study carried out enhancement a decoding speed by adaptation CRC with Turbo Code Algorithm, improvement of metric method, and reduction of decoding delay by using of Center-to-Top method. And the results are as follows: (1) Confirmed that a Turbo Code is so useful methods for reducing communication error in lots of noise environments. (2)Proposed technology in this study speed increasing method of Turbo Coding Algorithm proves 2 times faster than normal Turbo Code and communication error reducing as well in the board made by VHDL software & chips ALTERA company.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.10
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• pp.1111-1116
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• 2014

In this paper, in order to improve performance of LDPC codes, we propose an effective algorithm with lowering error floor of LDPC codes. This method is done by breaking trapping sets, mostly caused by an undesirable structure. This algorithm is not need to observe all the errors, only need to break the trapping sets, to effect the effectiveness. Simulation results show that its performance can be significantly improved with this decoding algorithm.

• Proceedings of the KIPE Conference
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• 1998.11a
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• pp.5-8
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• 1998

The adaptation to vector control theory is so generalized that it is widely used for implementing the high-performance of AC machine. Nowadays, One-Chip microprocessors or DSP chips are being well-used to implement Vector Control algorithm. DSP Chip have less flexibility for memory decoding and I/O rather than One-Chip microprocessor so that is requires more additional circuit and high cost. And the past One-Chip micro processors have difficult of implementation the complex algorithm because of small memory capacity and low arithmetic performance. Therefore we implemented the vector control algorithm of PMSM(Permanent Magnetic Synchronous Motors) using 80296SA form intel , which have many features as 6M memory space, 500MHz clock frequency, including memory decoding circuit and general I/O, Special I/O(EPA, Interrupt controller, Timer/Count, PWM generator) which is proper controller for the complex algorithm or operation program requiring so much memory capacity, So in this paper we fully digitized the vector control of PMSM included SVPWM Voltage controller using the intel 80296SA

• ETRI Journal
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• v.34 no.4
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• pp.629-632
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• 2012

This letter investigates the combination of the Chase-2 and sum-product (SP) algorithms for low-density parity-check (LDPC) codes. A simple modification of the tanh rule for check node update is given, which incorporates test error patterns (TEPs) used in the Chase algorithm into SP decoding of LDPC codes. Moreover, a simple yet effective approach is proposed to construct TEPs for dealing with decoding failures with low-weight syndromes. Simulation results show that the proposed algorithm is effective in improving both the waterfall and error floor performance of LDPC codes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.6
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• pp.57-62
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• 2011

In this paper an efficient LT decoding scheme using GE triangularization is proposed. The proposed algorithm has the desirable performance in terms of both overhead and computational complexity. Belief propagation algorithm is a fast and simple decoding scheme for LT codes. However, for a small code block length k, it requires a large overhead to decode, and OFG which has a small overhead has a large computational complexity. Simulation results show that the proposed algorithm noticeably reduces the computational complexity by more than 1/5 with respect to that of OFG and also its overhead has a small value about 1~5%.

• Journal of Korea Multimedia Society
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• v.7 no.1
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• pp.73-79
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• 2004

In this paper, we propose an efficient soft decision decoding algorithm for linear block codes. A conventional soft decision decoder have to invoke a hard decision decoder several times to estimate its soft decision values. However, in this method, we may not have candidate codewords, thus it is very difficult to produce soft decision values. We solve this problem by introducing an efficient algorithm to search candidate codewords. By using this, we can highly reduce the cases we cannot find candidate codewords. We estimate the performance of the proposed algorithm by using the computer simulations. The simulation is performed for binary (63, 36) BCH code in fading channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1548-1557
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• 1994

In this paper, the dual mode error correcting adaptive decoding algorithm which is adapted to the continuous phase frequency shift keying(CPFSK) modulation is presented as a technique for overcoming the distortion that reveals from the Rayleigh fading channel. The dual mode adaptive decoder nominally operates as a Viterbi decoder and switches to the burst error correcting mode, whenever the decoder detects an uncorrectable burst error pattern. Under the fading channel environment and when the usable memory quantity is restricted, the dual mode adaptive decoding algorithm shows an advantage in the BER performance over the interleaving technique, and also obtains the merit of not needing the large time delay that the interleaving technique requires. The experimental results from the computer simulation demonstrate the performance of the algorithm and verify the theoretical results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.8-14
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• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.