• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.23-31
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• 2010

The increasing demands on low-power, and low-complexity video encoder have been motivating extensive research activities on distributed video coding (DVC) in which the encoder compresses frames without utilizing inter-frame statistical correlation. In DVC encoder, contrary to the conventional video encoder, an error control code compresses the video frames by representing the frames in the form of syndrome bits. In the meantime, the DVC decoder generates side information which is modeled as a noisy version of the original video frames, and a decoder of the error-control code corrects the errors in the side information with the syndrome bits. The noisy observation, i.e., the side information can be understood as the output of a virtual channel corresponding to the orignal video frames, and the conditional probability of the virtual channel model is assumed to follow a Laplacian distribution. Thus, performance improvement of DVC systems depends on performances of the error-control code and the optimal reconstruction step in the DVC decoder. In turn, the performances of two constituent blocks are directly related to a better estimation of the parameter of the correlation channel. In this paper, we propose an algorithm to estimate the parameter of the correlation channel and also a low-complexity version of the proposed algorithm. In particular, the proposed algorithm minimizes squared-error of the Laplacian probability distribution and the empirical observations. Finally, we show that the conventional algorithm can be improved by adopting a confidential window. The proposed algorithm results in PSNR gain up to 1.8 dB and 1.1 dB on Mother and Foreman video sequences, respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.6
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• pp.84-89
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• 2003

In this paper, we real-time implemented to the TMS320C5416 the vocoder of variable bit rate applied the SOLA-B algorithm by Henja to the ITU-T G.729A vocoder of 8kbps transmission rate. This proposed method using the SOLA-B algorithm is that it is reduced the duration of the speech in encoding and is played at the speed of normal by extending the duration of the speech in decoding. At this time, we bandied that the interval of cross correlation function if skipped every 3 sample for decreasing the computational amount of SOLA-B algorithm. The real-time implemented vocoder of C.729A and SOLA-B algorithm is represented the complexity of maximum that is 10.2MIPS in encoder and 2.8MIPS in decoder of 8kbps transmission rate. Also, it is represented the complexity of maximum that is 18.5MIPS in encoder and 13.1MIPS in decoder of 6kbps, it is 18.5MIPS in encoder and 13.1MIPS in decoder of 4kbps. The used memory is about program ROM 9.7kwords, table ROM 4.5kwords, RAM 5.1 kwords. The waveform of output is showed by the result of C simulator and Bit Exact. Also, for evaluation of speech quality of the vocoder of real-time implemented variable bit rate, it is estimated the MOS score of 3.69 in 4kbps.

• Journal of Advanced Navigation Technology
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• v.10 no.4
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• pp.371-376
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• 2006

The initial radius of sphere decoder has great effect on the bit error rate performance and computational complexity. Until now, it has been determined either by considering the statistical property of channel or by using of MMSE solution. The initial radius obtained by using statistical property of channel includes the lattice point corresponding to the transmit signal vector with very high probability. The method using MMSE solution first calculates out the MMSE solution of the received signal, then maps the hard decision of this solution into the received signal space, and finally the distance between the mapped point and the received signal is selected as the initial radius of the sphere decoding. In this paper, we derive a simple equation for initial radius selection which uses statistical property of channel and compare it with the method using MMSE solution. To compare two methods we define new metric 'Tightness'. Through the simulation, we observe that in low and moderate SNR region, the method using MMSE solution provides more complexity reduction for decoding while in high SNR region, the method using channel statistics is better.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.24-31
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• 2010

A receiver architecture with low complexity for chirp spread spectrum (CSS) of IEEE 802.15.4a is proposed. To demodulate the received signal at the highest signal to noise power ratio, matched filter is generally adopted for the receiver of wireless communication systems. It is, however, not resonable to adjust the matched filter to the receiver of CSS whose objectives are low complexity, low cost and low power consumption since complexity of the matched filter is high. In this paper, we propose a new receiver architecture using differential multiplication and accumulator not matched filter for demodulation. Also, bi-orthogonal decoder implemented by only adder/subtractor is proposed. The hardware resources for implementation are reduced in the proposed receiver architecture, although bit error rate performance is low compared with the receiver architecture based on the matched filter.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.422-425
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• 2012

This paper proposes the CU-based approach for merge candidate list construction for providing reduced complexity and improved parallelism compared to the PU-based one. In the proposed method, a CU can have only one merge candidate list. So, Only one common merge candidate list is used for all PUs in a CU regardless of the PU partition type. The simulation results of proposed method showed that the encoder computational complexity was decreased by 3% to 6% and the decoder computational complexity was negligible change with the penalty of roughly 0.2% - 0.5% coding loss. The proposed method has several advantages: it provides simpler design, reduced complexity, and improved parallelism.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.148-154
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard are required a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method is reduced number of unnecessary iteration. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.498-512
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• 2010

Intra coding is an indispensable coding tool since it can provide random accessibility as well as error resiliency. However, it is the problem that intra coding has relatively low coding efficiency compared with inter coding in the area of video coding. Even though H.264/AVC has significantly improved the intra coding performance compared with previous video standards, H.264/AVC encoder complexity is significantly increased, which is not suitable for low bit rate interactive services. In this paper, a Voting-based Intra Mode Bit Skip (V-IMBS) scheme is proposed to improve coding efficiency as well as to reduce encoding time complexity using decoder-side prediction. In case that the decoder can determine the same prediction mode as what is chosen by the encoder, the encoder does not send that intra prediction mode; otherwise, the conventional H.264/AVC intra coding is performed. Simulation results reveal a performance increase up to 4.44% overall rate savings and 0.24 dB in peak signal-to-noise ratio while the frame encoding speed of proposed method is about 42.8% better than that of H.264/AVC.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.499-502
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• 2006

H.264/MPEG4 Advanced Video coding joint standard needs deblocking filter of decoder. We propose a better deblocking algorithm ensuring picture quality even if it is low bit-rate and bandwidth in MPEG-4 video. The complexity diminishes in proposed deblocking algorithm because it uses only simple shift, addition and comparison. We handle dividing into complexity area, medium area and simple area after counting boundary intensity of mask block to identify presence of block effects. As a result of experiment, we make certain of that block effects reduces in proposed deblocking algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.1987-2001
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• 2017

Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.