• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.488-496
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• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• Journal of Communications and Networks
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• 제16권6호
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• pp.620-626
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• 2014

In this paper, we propose a parallel collaborative sphere decoder with a scalable architecture promising quasi-maximum likelyhood performance with a relatively small amount of computational resources. This design offers a hardware-friendly algorithm using a modified node operation through fixing the variable complexity of the critical path caused by the sequential nature of the conventional sphere decoder (SD). It also reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by tree pruning using collaboratively operated node operators. A Monte Carlo simulation shows that our proposed design can be implemented using only half the parallel operators compared to the approach using an ideal fully parallel scheme such as FSD, with only about a 7% increase of the normalized decoding time for MIMO dimensions of $16{\times}16$ with 16-QAM modulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• 한국통신학회논문지
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• 제39A권4호
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• pp.180-187
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• 2014

본 논문에서는, 하향 다중 사용자 MIMO 환경에서 간섭 검출 및 제거를 하기위해 확장된 fixed-complexity sphere decoder (FSD) 알고리즘이 제안되었다. 제안된 알고리즘은, generalized sphere decoder (GSD) 알고리즘을 이용한 채널행렬 확장과 간섭신호와 요구신호를 고려한 채널행렬 순서화를 통해 FSD 알고리즘을 간섭신호 검출에 활용 가능하도록 확장 하였다. IEEE802.11ac의 통신모드 중 네 명의 다중 사용자에게 각각 702 Mbit/s 전송이 가능한 환경의 몬테카를로실험을 통해서, 제안된 알고리즘이 10% packet error rate기준으로 간섭제거 기능이 없는 maximum-likelihood 검출성능 대비 $E_b/N_0$가 약 3 dB 향상됨을 보여주었다.

• 한국통신학회논문지
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• 제31권4C호
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• pp.303-309
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• 2006

By combining the space-time diversity technique and iterative turbo codes, space-time turbo codes(STTCS) are able to provide powerful error correction capability. However, the multi-path transmission and iterative decoding structure of STTCS make the decoder very complex. In this paper, we propose a low complexity decoder, which can be used to decode STTCS as well as general iterative codes such as turbo codes. The efficient implementation of the backward recursion and the log-likelihood ratio(LLR) update in the proposed algorithm improves the computational efficiency. In addition, if we approximate the calculation of the joint LLR by using the approximate ratio(AR) algorithm, the computational complexity can be reduced even further. A complexity analysis and computer simulations over the Rayleigh fading channel show that the proposed algorithm necessitates less than 40% of the additions required by the conventional Max-Log-MAP algorithm, while providing the same overall performance.

• 방송공학회논문지
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• 제15권1호
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• pp.112-121
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• 2010

분산 동영상 코딩(Distributed Video Coding)은 기존의 동영상 코딩과 다르게 인코더와 디코더 사이의 복잡도 분배가 가능한 새로운 코딩 방식이다. 본 논문에서는 단계적 움직임 예측을 이용하여 인코더와 디코더의 복잡도를 분배하는 방법을 제안한다. 인코더에서는 부분적으로 움직임 예측을 수행하여 그 결과를 디코더로 전송하고, 디코더는 이를 받아 좁혀진 범위 내에서 남은 움직임 예측을 수행하게 된다. 인코더에서 어느 정도 복잡도를 감당할 수 있을 때 인코더와 디코더 사이의 복잡도 분배 비율의 조절이 가능하다. 이를 통해 복잡도 분배 비율과 압축효율과의 상관성을 알아볼 수 있는데, 인코더의 복잡도 상승에 의한 압축효율 향상율이 디코더 복잡도 상승에 의한 압축효율 향상율보다 훨씬 크다는 것을 알 수 있다. 제안 방법을 통해 단말기의 성능이나 채널 상황에 따라 인코더와 디코더 사이의 복잡도를 적응적으로 분배하고 그에 따라 코딩 성능을 조절할 수 있다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.890-893
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• 2008

In this paper, we present a low complexity modified multi-level sphere decoder (SD) for multiple-input multiple-output (MIMO) systems employing quadrature amplitude modulation (QAM) signals. The proposed decoder, exploiting the multi-level structure of the QAM signal scheme, first decomposes the high-level constellation into low-level 4-QAM constellations, so-called sub-constellations. Then, it deploys SD in the sub-constellations in parallel. In addition, in the searching stage, it uses the optimal low-complexity sort method. Computer simulation results show that the proposed decoder can provide near optimal maximum-likelihood (ML) performance while it significantly reduces the computational load.

• 한국통신학회논문지
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• 제22권7호
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• pp.1419-1426
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• 1997

A new SCEE(Syndrome Check Error Estimation) decoding method for convolutional code and concatenated SCEE/RS (Reed-Solomon) conding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are drived when some combination of predecoder-reencoder is used. Computer simulation results show that the compuatational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi-decoder without degratation of the $P_{e}$ performance. Also, the concatenated SCEE/RS decoder has almost the same complexity of a RS decoder and its coding gain is higher than that of soft decision Viterbi or RS decoder respectively.

• Journal of Multimedia Information System
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• 제4권4호
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• pp.179-188
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• 2017

The Internet Video Coding (IVC) standard is due to be published by Moving Picture Experts Group (MPEG) for various Internet applications such as internet broadcast streaming. IVC aims at three things fundamentally: 1) forming IVC patents under a free of charge license, 2) reaching comparable compression performance to AVC/H.264 constrained Baseline Profile (cBP), and 3) maintaining computational complexity for feasible implementation of real-time encoding and decoding. MPEG experts have worked diligently on the intellectual property rights issues for IVC, and they reported that IVC already achieved the second goal (compression performance) and even showed comparable performance to even AVC/H.264 High Profile (HP). For the complexity issue, however, there has not been thorough analysis on IVC decoder. In this paper, we analyze the IVC decoder in view of the time complexity by evaluating running time. Through the experimental results, IVC is 3.6 times and 3.1 times more complex than AVC/H.264 cBP under constrained set (CS) 1 and CS2, respectively. Compared to AVC/H.264 HP, IVC is 2.8 times and 2.9 times slower in decoding time under CS1 and CS2, respectively. The most critical tool to be improved for lightweight IVC decoder is motion compensation process containing a resolution-adaptive interpolation filtering process.