• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.353-356
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• 2002

In this paper, we design an efficient, scalable one-dimensional discrete wavelet transform (1DDWT) filter using data reorder unit (DRU). At each level, the required hardware is optimized by sharing multipliers and adders because the input rate is reduced by a factor of two at each level due to decimation. The proposed architecture shows 100% hardware utilization by balancing hardware with input rate. Furthermore, sharing the coefficients of the highpass and the lowpass filters using the mirror filter property reduces the number of multipliers and adders by half. We designed a scalable DRU that efficiently reorders and feeds inputs to highpass and lowpass filters. The proposed DRU-based architecture is so regular and scalable that it can be easily extended to an arbitrary 1D DWT structure with M taps and J levels. Compared to other architectures, the proposed DWT filter shows efficiency in performance with relatively less hardware.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.407-416
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• 2000

Adaptive digital filtering and noise cancelling technique using a tree structured filter bank are presented to reduce a undesirable aliasing due to the decimation of filtered output and improve the performance in terms of mean-square error and the convergence speed using a aliasing canceller. A signal is split into two subband by analysis filter bank and decimated by decimator and reconstructed by interpolation technique and synthesis filter bank. A variable step-size LMS algorithm is used to improve the convergence speed in case of existing the measurement noise in desired input of filter. It is shown by computer simulation that the proposed subband structure in this paper is superior to conventional subband filter structure in terms of mean-square error and convergence speed.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.4 s.304
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• pp.153-158
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• 2005

In this paper, a filter is proposed to compensate droop of the CIC filter for SDR. The proposed compensation filter has almost linear-phase characteristic, requires low operational complexity, and is cost-effective due to its second-order characteristic and lowest operational rate in the baseband.. Especially, it compensates droop in the passband with little performance degradation in the stopband. It is shown, by a design example and its performance analysis, that the proposed compensation method gives performance enhancement in communication systems. It is also shown that the proposed method is superior to conventional ones in view of memory usage and computational load.

• Journal of the Korea Institute of Military Science and Technology
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• v.22 no.3
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• pp.332-340
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• 2019

Electronic warfare systems are needed to be advantageous in the modern war. Many radar threat signals with various frequency spectrums and complicated techniques exist. For detecting the threats, a receiver with wide and narrow-band digital processing is needed. To process a wide-band searching mode, a polyphase filter bank has become the architecture of choice to efficiently detect threats. A polyphase N-path filter aligns the re-sampled time series in each path, and a discrete Fourier transform aligns phase and separates the sub-channel baseband aliases. Multiple threats and CW are detected or rejected when the signals are received in different sub-channels. And also, to process a narrow-band precision mode, a direct down converter is needed to reduce aliasing by using a decimation filter. These digital logics are designed in a FPGA. This paper shows how to design and develop a wide and narrow-band digital receiver that is capable to detect the threats.

• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.348-352
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• 2017

In this paper, we propose a high resolution A/D converter for a sensor interface that processes low frequency AC signals. A 6b SAR ADC with low power consumption and a 11b incremental ADC with high resolution are combined together to perform 15b resolution. Conventional hybrid ADC has a disadvantage that it can convert t only DC signal, but in this paper, it is possible to convert data to AC signal by increasing input range of incremental ADC. The decimation filter is implemented on-chip. The designed Hybrid ADC operates at supply voltage of 1.8V and consumes the current of 6.98uA. The OSR (oversampling ratio) is 90. And SFDR, SNDR, ENOB and FoMs are 96.59dB, 88.47dB, 14.4-bit and 139.5dB, respectively.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• fall
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• pp.180-182
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• 2021

본 논문에서는 드론의 비행 장소와 온도 및 습도에 영향을 받지 않는 적외선 기반 깊이 카메라로부터 얻어진 깊이영상을 분석하여 지면 영역을 찾고 AGL(Above Ground Level) 단위의 고도를 측정하는 방법을 제안한다. Decimation filter 와 Median filter 를 적용하여 잡음 및 빈 데이터들을 제거한 깊이영상으로부터 RANSAC (RANdom Sample Consensus) 기반 평면 모델 추정 방법을 이용하여 지면 영역과 이에 대한 평면의 방정식을 유추하고 현재 위치와의 거리를 계산한다. 성능 평가를 위해 Lidar 센서와 비교한 결과, 제안 방법이 지면에 위치한 장애물에 영향을 더 적게 받으며, 자세 정보와 독립적으로 고도를 측정할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.150-158
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• 2010

Filtering is necessary for the SRC(sample rate converter), that is used to change the sampling rate of a digital signal. The larger the conversion ratio of the sampling rate becomes, the more signal processing is needed for the filter, which means more complexity on realization. Thus it is important to reduce the amount of signal processing for the case of substantial conversion ratios. In this paper it is presented an efficient design method of a multistage FIR(finite impulse response) filter, with which the rate conversion occurs in stages rather than in one step. In this method, filter searching is performed exhaustively over all possible factorization of the conversion ratio, and also the filter complexity is measured based on direct realization rather than on estimation. It has been shown a designed multistage filter to have a less number of multiplications for filtering operation in comparison with a conventionally designed one. It has also been found that by allowing some variations of the filter architecture such as a halfband filter or a filter with multiple transition bands, the number of multiplications can be reduced further.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1170-1177
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• 1997

Morphology is a shape preseving filter. Several morphology filter can be made by the combination of morphological basic operation. If we use morphology filter in decimation process for a hierarchical encoder, there are some advantagesin reduction aliasing effects. In this paper, we propose a new hierarchical coder with morphological filtering and vector quantization. And then, firstly, we confirm that CO filtering is the best one among the 4 kinds of morphology filters to reduce aliasing effects in Laplacian pyramid transmission proposed by Burt. Secondly, the those two coders was compared. The results of our simulation show that our new coder surpasser the Laplacian pyramid especially in complex images.