• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.12
• /
• pp.155-160
• /
• 2003

Owing to the advances in ADC and DSP technologies, signals in If band, which once had to be processed in analog technology, can new be digitally processed. This is referred to as "Digital IF" or "Digital Radio", which is a preliminary stage of SDR. Applying the digital radio technology to a multi-carrier receiver design, a processing gain is generated through an over-sampling of input data. In the digital receiver, decimation is performed for reducing the computational complexity CIC and half band filter is used together with the decimation as an anti-alising filter. The CIC filter, however, should introduce the roll-off phenomenon in the passband, which causes the receiving performance to be considerably degraded due to the distorted Passband flatness of receiving filter. In this paper, we designed a CIC roll-off compensation filter for W-CDMA digital receiver. The performance of the proposed compensation filter is confirmed through computer simulations in such a way that the BER is minimized by compensating the roll-off characteristics.off characteristics.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.10
• /
• pp.169-177
• /
• 2012

A non-decimation second-order spatial moving average (SMA) discrete-time (DT) filter is proposed with reconfigurable null frequencies. The filter coefficients are changeable, and it can be controlled by switching sampling capacitors. So, interferers can be rejected effectively by flexible nulls. Since it operates without decimation, it does not change the sample rate and aliasing problem can be avoided. The filter is designed with variable weight of coefficients as $1:{\alpha}:1$ where ${\alpha}$ varies from 1 to 2. This corresponds to the change of null frequencies within the range of fs/3~fs/2 and fs/2~2fs/3. The proposed filter is implemented in the TSMC 0.18-${\mu}m$ CMOS process. Simulation shows that null frequencies are changeable in the range of 0.38~0.49fs and 0.51~0.62fs.

• Journal of Satellite, Information and Communications
• /
• v.5 no.1
• /
• pp.32-37
• /
• 2010

The algorithm of multiple channel signal processing requires the flexibility of variable frequency band, efficient allocation of transmission power, and flexible frequency band reallocation to satisfy various service types which requires different transmission rates and frequency band. There are three methods including per-channel approach, multiple tree approach, and block approach performing frequency band reallocation method by channelization and dechannelization in the multiple-channel signal. This paper proposes an improved per-channel approach for converting the frequency band of multiple carrier signals efficiently. The proposed algorithm performs decimation and interpolation using CIC(cascaded integrator comb filter), half-band filter, and FIR filter. In addition, it performs filtering of each sub-channel, and reallocates channel band through FIR low-pass filter in the multiple-channel signal. The computer simulation result shows that the perfect reconstruction of output signal and the flexible frequency band reallocation is performed efficiently by the proposed algorithm.

• Journal of the Institute of Convergence Signal Processing
• /
• v.7 no.2
• /
• pp.65-72
• /
• 2006

In digital signal processing, the polyphase decomposition of signal has been often used in the implementation of multirate system. Especially, in the design of digital filter and so forth the method in very useful to improve the performance of various algorithms because it provides the multi-channel for paralled processing. Generally, the polyphase-decomposed signals tend to expand the frequency band by including more high frequencies than original signal from decimation for down sampling. This property brings about the significant limitation in the structure or the performance of digital polyphase signal processing system. In this paper we theoretically propose a perfect band compression and reconstruction method for polyphase component signals, then experimentally show its effectiveness through Matlab simulation.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.42 no.5 s.305
• /
• pp.145-156
• /
• 2005

In application for acoustic echo cancellation and adaptive equalization, input signal is highly correlated and the long length of adaptive filter is needed. Affine projection algorithms, in these applications, can produce a good convergence performance. However, they have a drawback that is a complex hardware implementation. In this paper, we propose a new subband affine projection algorithm with improved convergence and reduced computational complexity. In addition, we suggest a good approach to implement the proposed method. In this method by applying polyphase decomposition, noble identity and critical decimation to the anne projection algorithm the number of input vectors for decorrelation can be reduced. The weight-updating formula of the proposed method is derived as a simple form that compared with the NLMS(normalized least mean square) algorithm by the reduced projection order The efficiency of the proposed algorithm for a colored input signal was evaluated by using computer simulations.

• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.497-500
• /
• 2003

In this paper, a new filter structure to improve frequency response characteristics in CIC(Cascaded Integrator-Comb) decimation filters is proposed. Conventional filters improve passband characteristics, but they make worse slinging band characteristics. In this paper, we propose a new filter which is called IFOP(Interpolated Fourth-Order Polynomials). By using this proposed filter, passband droop and aliasing band attenuation are simultaneously improved. Since proposed filter needs only one multiplication computation is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, implementation cost of the proposed filter is compared with those of conventional filters.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.37 no.5
• /
• pp.115-123
• /
• 2000

In this paper, a block FIR(Finite Impulse Response) filtering architecture is proposed for IF digital down converter. Digital down converter consists of digital mixers. decimation filters and down samplers. In this proposed structure, it is shown that a efficient parallel decimation filter architecture can be produced by cancellation of inherent up sampling of the block filter and following down sampler Furthermore. it is shown that computational complexity of the proposed architecture is reduced by exploiting the block FIR structure and zero values of the digital mixers.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.20 no.4
• /
• pp.10-15
• /
• 1983

In this paper effective methods of demodulation and equalization in a 9600 bps modem have been studied. To reduce the number of multiplications required per symbol in demodula-tion, the method of using a decimation filter is presented. In the equalizer the optimum step size and the steady state mean-squared error (MSE) are obtained from computer simulation results. The performance of the first-order carrier phase tracking loop is compared with that of the second-order loop when carrier frequency offset exists. In addition, the finite word length effects in the equalizer are studied.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.12
• /
• pp.2227-2232
• /
• 2007

In this paper, it is presented a Real FFT for the FMCW radar distance measurement with high resolution. The high distance resolution needs the measurement of the accurate beat frequency. To improve the distance resolution, zoom fft, decimation, digital low pass filter and zero padding method are used. The simulation results using the Matlab show ${\pm}5mm$ of distance resolution and the measuring range is up to 35meter.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2001.10a
• /
• pp.711-714
• /
• 2001

본 논문에서는 파이프라인 구조를 이용하여 고성능 1 차원 이산 웨이블렛 변환 필터를 설계하였다. 각 레벨에서 입력이 다운샘플링(downsampling, decimation)되므로 각 레벨의 하드웨어를 폴딩(folding) 기법을 이용하여 곱셈기와 덧셈기를 공유함으로써 복잡도를 개선하였다. 즉, 제안한 구조에서는 레벨 2 와 레벨 3 에서 폴딩된 구조의 C.S.R(Circular Shift Register)곱셈기와 덧셈기를 사용함으로써 하드웨어 효율(hardware utilization)을 각 레벨에서 100%로 높일 수 있다. 또한, 홀수와 짝수의 샘플을 병렬로 입력함으로써 단일 입력의 시스템과 비교할 때, 동일 시간에 병렬화 만큼의 이득을 얻을 수 있었고, 필터 계수는 미러 필터(mirror filter)의 특성을 이용하여 쳐대한 고역 필터(high pass filter)와 저역 필터(low pass filter)의 계수들을 공유함으로써 곱셈기와 덧셈기의 수를 반으로 줄였다. 그리고 임계 경로(critical path)를 줄이기 위한 파이프라인 레지스터를 삽입하여 고성능 시스템을 구현하였다.