• The Journal of the Korea Contents Association
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• v.9 no.1
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• pp.89-97
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• 2009

The use of database system in application increases day by day. This brought out the DBMS interconnection access problem with rapid increase of the user. To solve these database connection problem, database connection pool has been presented. However, there is much to be desired on user's interconnection access. To improve previous connection pool architecture, we have designed the sub connection pool besides main connection pool in this paper. We defined connection pool broker to manage both main and sub connection pool connection. When main connection pool reached its limitation, connection pool broker transfers a connection from a main connection pool to a sub connection pool. When the interconnection access user increased rapidly, we have proved that the suggested sub pool architecture is more effective on response time by comparing it with other existing DBMS connection pool architectures using simulation.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05c
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• pp.1507-1510
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• 2003

웹 어플리케이션 개발 시 데이터베이스 시스템의 사용이 증가함에 따라 데이터베이스 시스템에 접속하는 커넥션 리소스 관리에 대한 중요성이 부각되고 있다. 본 논문은 웹 어플리케이션 구축 시 사용하는 데이터베이스 접속 풀(Database connection Pool)의 성능을 평가하고 진단하는 도구를 제안한다. 본 도구는 성능 및 진단을 통하여 웹 어플리케이션에 가장 적합한 최적화된 DB 커넥션 풀을 최적화하는 방법을 제시한다. 아울러 제안된 도구를 사용한 효과적인 데이터베이스 접속 풀(Database Connection Pool)의 관리 결과에 대하여 기술한다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2008.06a
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• pp.125-130
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• 2008

어플리케이션의 데이터베이스 시스템 사용이 증가하면서, 사용자 급증에 따른 데이터베이스 시스템에 동시접속 하는 커넥션 처리 방법에 있어 중요성이 부각되고 있다. 이러한 데이터베이스의 커넥션을 효과적으로 처리하기 위해 데이터베이스 커넥션 풀이 도입되었으나, 동시접속이 증가하는 형태에 따른 커넥션 처리는 미비한 실정이다. 이 논문에서는 기존의 커넥션 아키텍처를 개선하여 주 커넥션 풀과 보조 커넥션 풀, 두 커넥션 풀의 연결을 할당하기 위한 커넥션 브로커 관계에 있어 새로운 아키텍처를 정의하였고, 실험을 통하여 기존 데이터베이스 커넥션 풀 구조와 비교해서 100% 가량 성능이 향상된 결과를 제시하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.69-75
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• 2016

The performance of a web application is an essential issue to provide high quality of the services in interactive web environments. On a sudden increase in traffic in a very short span of time, the servers became CPU starved and would become unresponsive. This would lead to a bad experience for the clients of web service. This paper deals with the effects of two configurable software settings of J2EE application servers: the maximum size of the thread pool and the maximum size of database connection pool. In order to figure out the optimum configuration value, this paper builds experimental evaluation method for web performance analysis. Finally, a case study related with the proper experimental method is presented with performance result.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.139-141
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• 2006

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nano-electronic devices which will inherit the throne of CMOS which is the domineering implementation technology of large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors. After the gate and interconnect structures of the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit QCA adder. The digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• IE interfaces
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• v.25 no.1
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• pp.21-30
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• 2012

In the past, buyers and suppliers met each other to find common interests off-line in exhibitions and conferences, or through personal connection. These activities were time consuming and costly. With the advent of information era, these activities moved to online market places, where buyers search for suppliers with a set of keywords that are believed to be representative of their requirements. Its fundamental assumption is that all the potential candidates are registered in a certain database. However, recently buyers want to diversify suppliers due to needs of cost competitiveness or frequent new product development. To this end, instead of choosing suppliers from the supplier pool, discovering suppliers from all over the world should be emphasized. In order to enable buyers to describe their requirements and suppliers to capture their manufacturing capabilities via online market places, the semantic differences of terms between buyers and suppliers should be resolved. The paper summarizes various supplier discovery frameworks and prototype systems, which can be employed to expose domestic small-medium enterprises into global buyers in the near future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.