• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.193-199
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• 2008

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.5
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• pp.353-363
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• 1990

This paper analyzes effect of Data Bit Jitter(DBJ) on the Bit Slip Rate(BSR) of the receiver Data Tracking Loop(DTL). In particular, we point out the characteristic jitter parameters that can be used to estimate the BSR performance for the low frequency parts respectively. We also propose a new format for the DBJ specification, which is more sophisticated than the conventional method but is believed to be more practical and accurate in predicting DBJ effect on the receiver BSR performance. In the proposed method, receive dependent parameters are identified and weighting between different parts of jitter spectrum are properly considered.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.5
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• pp.583-586
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• 2004

Transition jitter noise is one of major sources of detection errors in high density recording channels. Implementation complexity of the optimal detector for such channels is high due to the data dependency and correlated nature of the jitter noise. In this paper, two types of hardware efficient sub-optimal detectors are derived by modifying branch metric of Viterbi algorithm and applied to partial response (PR) channels combined with run length limited modulation coding. The additional complexity over the conventional Viterbi algorithm to incorporate the modified branch metric is either a multiplication or an addition for each branch metric in the Viterbi trellis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.34-39
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• 2007

Serial links via backplane channels suffer from severe signal integrity problems which are normally caused by channel imperfections, such as flat loss, frequency-dependent loss, reflection, etc. Particularly, the frequency-dependent loss causes ISI(Inter-Symbol-Interference) at signal waveforms. Therefore, adaptive equalizing techniques have been exploited in many products to facilitate the ISI problem. In this paper, we present an analog adaptive equalizer circuit designed in a $0.18{\mu}m$ CMOS process. It achieves 10Gb/s data transmission through a long 34-inch backplane channel(or transmission line). The post-layout simulations demonstrate $8ps_{p-p}$ jitter with 10mW power dissipation. The core of the adaptive equalizer occupies the area of $0.56mm^2$.