• 전자공학회논문지A
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• 제33A권5호
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• 대한전자공학회논문지
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• 제25권7호
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• pp.851-858
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• 1988

In this paper, we propose two different VLSI architectures for the parallel computation of DCT (discrete cosine transform) algorithm. First, it is shown that the DCT algorithm can be implemented on the existing systolic architecture for the DFT(discrete fourier transform) by introducing some modification. Secondly, a new prime factor DCT algorithm based on the prime factor DFT algorithm is proposed. And it is shown that the proposed algorihtm can be implemented in parallel on the systolic architecture for the prime factor DFT. However, proposed algorithm is only applicable to the data length which can be decomposed into relatively prime and odd numbers. It is also found that the proposed systolic architecture requires less multipliers than the structures implementing FDCT(fast DCT) algorithms directly.

• 산업경영시스템학회지
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• 제29권3호
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• pp.79-86
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• 2006

Especially, MTO(Make-To-Order) companies take collaborative approaches with their partner companies to make low-price products and/or technologically low intensive products. The collaborative approach to manufacturing requires collaboration with partner companies for inventory review, production plan, and manufacturing to fulfill customer's orders. However, frequent changes of partnerships binder partner companies from sharing production information in effective ways since their information systems have different data architectures and platforms. Therefore, it is required flexible and standardized system integration approach fir effective information sharing. This research studies current status and problems of collaborative production system, proposes an architecture for collaborative production systems based on Web Services which is a standard information technology, and discusses expected effects and the vision of Web Services.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권1호
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• pp.248-268
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• 2018

The performance of smartphone applications are usually constrained in user interactions due to resource limitation and it promises great opportunities to improve the performance by exploring the smartphone built-in and embedded sensing techniques. However, heterogeneity in techniques, semantic gap between sensor data and usable context, and complexity of contextual situations keep the techniques from seamless integration. Relevant studies mainly focus on feasibility demonstration of emerging sensing techniques, which rarely address both general architectures and comprehensive technical solutions. Based on a proposed functional model, this investigation provides a general architecture to deal with the dynamic context for context-aware automation and decision support. In order to take advantage of the built-in sensors to improve the performance of mobile applications, an ontology-based method is employed for context modelling, linguistic variables are used for heterogeneous context presentation, and semantic distance-based rule matching is employed to customise functions to the contextual situations. A case study on mobile application authentication is conducted with smartphone built-in hardware modules. The results demonstrate the feasibility of the proposed solutions and their effectiveness in improving operational efficiency.

• 천문학회보
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• 제42권1호
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• pp.53.4-53.4
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• 2017

With large-volume surveys becoming the norm, it is increasingly important to accurately model the galaxy-halo connection and being able to create mock universes of galaxies - starting from dark matter halo catalogs - that reproduce with high-fidelity all the characteristics of a given experiment. This step is necessary, in order to safely interpret cosmological data and fully control systematic effects. We are developing a new Python-based tool which integrates several existing packages and allows one to reproduce many of the forms used to describe galaxy-halo models, ranging from halo occupation distribution (HOD) to abundance matching techniques, along with the characteristics of a given survey and the main testable observables. We are making the code parallel for high-performance parallel-architectures.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.235-238
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• 2002

This paper proposes a novel scheme of designating non-cacheable addresses of memories in embedded systems of multi-master architectures without a Memory Management Unit (MMU). As a solution for data coherency problem between external memories and a cache memory, we proposes a cache masking scheme by allocating the most significant bit of address not used in 32-bit address system as indicator bit to designate non-cacheable address. As this scheme enables non-cacheable area designation every address, the simpler in the aspect of hardware and more flexible size of non-cacheable area can be obtained.

• 경영정보학연구
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• 제3권2호
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• pp.277-288
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• 2001

Of critical importance to the success of any e-commerce site are the two factors: rapid application development and quick response time. A three-tier architecture composed of presentation layer, business layer, and data access layer emerges to allow rapid changes in user interface, business logic, and database structures. Too often, such a logical three-tier architecture is considered as requiring a three-tier physical architecture: Web server, application server, and database server running on separate computers. Contrary to the common belief, a Web stress test reveals that the three-tier logical architecture implemented on a two-tier physical platform guarantees a quicker response time due to the reduction in cross-machine communications. This would lead business firms to economize their spending on e-commerce: increasing the number of physical servers to expedite transaction is not necessarily the best solution. Before selecting a particular hardware configuration, a Web stress test needs to be conducted to compare the relative merits of alternative physical architectures. Together with capacity planning, Web stress test emerges as a powerful tool to build robust, yet economical e-commerce sites.

• 한국군사과학기술학회지
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• 제14권4호
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• pp.598-606
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• 2011

The importance of avionics systems has increased to a significant level in modern aircraft development. Modern avionics system is a complex integrated system of state-of-art hardware and software technology. Specifying the avionics system architecture is the most important task throughout the avionics system design process. This paper reviews modern avionics system architectures and proposes an effective avionics architecture suitable for modern attack helicopters.

• Journal of Electrical Engineering and Technology
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• 제6권3호
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• pp.418-422
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• 2011

For low-power sensor networks, a compact design of advanced encryption standard (AES) algorithm is needed. A very small AES core for ZigBee devices that accelerates computation in AES algorithms is proposed in this paper. The proposed AES core requires only one S-Box, which plays a major role in the optimization. It consumes less power than other block-wide and folded architectures because it uses fewer logic gates. The results show that the proposed design significantly decreases power dissipation; however, the resulting increased clock cycles for 128-bit block data processing are reasonable for IEEE 802.15.4 standard throughputs.