• Journal of Electrical Engineering and Technology
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• 제6권4호
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• pp.573-579
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• 2011

To meet the scalability and performance requirements of data analyses, which often involve voluminous data, efficient parallel or concurrent algorithms and frameworks are essential. We present a high-performance Korean morphological analyzer which employs the MapReduce framework on the graphics processing unit (GPU). MapReduce is a programming framework introduced by Google to aid the development of web search applications on a large number of central processing units (CPUs). GPUs are designed as a special-purpose co-processor. Their programming interfaces are typically formulated for graphics applications. Compared to CPUs, GPUs have greater computation power and memory bandwidth; however, GPUs are more difficult to program because of the design of their architectures. The performance of the Korean morphological analyzer using the MapReduce framework on the GPU is evaluated in comparison with the CPU-based model. The proposed Korean Morphological analyzer shows promising scalable performance on distributed computing with the GPU.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.477-483
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• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

• 전자공학회논문지C
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• 제34C권3호
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• pp.23-36
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• 1997

In tis paper, sthe new data model for the hardware implementation of lempel-ziv compression algorithm was proposed. Traditional model generates the codeword which consists of 3 bytes, the last symbol, the position and the matched length. MSB (most significant bit) of the last symbol is the comparession flag and the remaining seven bits represent the character. We confined the value of the matched length to 128 instead of 256, which can be coded with seven bits only. In the proposed model, the codeword consists of 2 bytes, the merged symbol and the position. MSB of the merged symbol is the comression flag. The remaining seven bits represent the character or the matched length according to the value of the compression flag. The proposed model reduces the compression ratio by 5% compared with the traditional model. The proposed model can be adopted to the existing hardware architectures. The incremental factors of the compression ratio are also analyzed in this paper.

• 전자통신동향분석
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• 제35권4호
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• pp.34-41
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• 2020

The existing Von Neumann architecture places limits to data processing in AI, a booming technology. To address this issue, research is being conducted on computing architectures and artificial neural networks that simulate neurons and synapses, which are the hardware of the human brain. With high-speed, high-throughput data communication infrastructures, photonic solutions today are a mature industrial reality. In particular, due to the recent outstanding achievements of artificial neural networks, there is considerable interest in improving their speed and energy efficiency by exploiting photonic-based neuromorphic hardware instead of electronic-based hardware. This paper covers recent photonic neuromorphic studies and a classification of existing solutions (categorized into multilayer perceptrons, convolutional neural networks, spiking neural networks, and reservoir computing).

• 한국석유지질학회:학술대회논문집
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• 한국석유지질학회 1999년도 제6차 학술발표회 발표논문집
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• pp.2-16
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• 1999

This study includes structural analysis of the northern Pattani Basin, areal description of depositional facies, and their spatial relationships using 3-D seismic and well data. Well log data indicate that the representative depositional facies of the studied intervals are sandy, fluvial, channel-fill facies encased in shaly floodplain deposits. Seismic responses were predicted from a synthetic seismogram using a model of dominant depositional facies. Peak-to-trough amplitude and instantaneous frequency seismic attributes are used in depositional facies interpretation. Three Intervals A, B and C are interpreted on the successive stratal surfaces. The shallowest interval, A, is the Quaternary transgressive succession. Each stratal surface showed flow pattern variation of fluvial channel facies. Two transgressive cycles were identified in interval A. Interval B also indicated fluvial facies. Depositional facies architectures are described by interpreting seismic attributes on the successive stratal surfaces.

• 한국통신학회논문지
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• 제42권1호
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• pp.8-13
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• 2017

Compare with other communication system based RF technology, Optical Camera Communication (OCC) has limitation on data rate due to the low frame rate of camera. The limitation on data rate can be solved with multiple-input and multiple-output (MIMO) technology; and it is the final target of all researches on OCC. The MIMO topology can be implemented easily without breaking out the architecture of image sensor. For image sensor classification, there are two architectures have been developed: rolling shutter and global shutter. The operation of two techniques is different so the performance is also different. In this paper we analyze and evaluate the performance of the MIMO architecture for OCC.

• 한국컴퓨터정보학회:학술대회논문집
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• 한국컴퓨터정보학회 2014년도 제49차 동계학술대회논문집 22권1호
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• pp.1-4
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• 2014

Although physical modeling synthesis is becoming more and more efficient in rich and natural high-quality sound synthesis, its high computational complexity limits its use in portable devices. This constraint motivated research of single-instruction multiple-data many-core architectures that support the tremendous amount of computations by exploiting massive parallelism inherent in physical modeling synthesis. Since no general consensus has been reached which grain sizes of many-core processors and memories provide the most efficient operation for sound synthesis, design space exploration is conducted for seven processing element (PE) configurations. To find an optimal PE configuration, each PE configuration is evaluated in terms of execution time, area and energy efficiencies. Experimental results show that all PE configurations are satisfied with the system requirements to be implemented in portable devices.

• 의료ㆍ복지 건축 : 한국의료복지건축학회 논문집
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• 제14권4호
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• pp.21-30
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• 2008

Domestic hospital architectures were developed with the nation's industrialization after 1960s. Particularly, with the rapidly growing healthcare demands according to The National Health Insurance Plan which was introduced in 1977 and expanded to entire nation in 1989, the number of healthcare facility is also increasing according to the expansion of the existing facilities and construction of new buildings. Now, twenty to thirty years were past since that growing period of healthcare architecture. Many hospitals are facing on the phase of restructuring and modernization for their resources. J university hospital is a representative case of hospital development which the growth of facility was stopped by insufficient site area. This study, analysing its past statistics and drawing data of that hospital, presents the characteristics of the changes and basic data of the master planning for the future hospital development.

• 전자통신동향분석
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• 제38권4호
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• pp.70-80
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• 2023

In recent years, our society has shifted from an information society to an intelligent information society, in which computing has become a key factor in shaping and driving social development. In this new era of digital civilization powered by the Internet of Things, traditional data-based computing is no longer sufficient to meet the growing demand for higher levels of intelligence. Therefore, intelligent computing has emerged, reshaping traditional computing and forming new computing paradigms to promote the digital revolution in the era of the Internet of Things, big data, and artificial intelligence. Intelligent computing has greatly expanded the scope of computing through new computing theories, architectures, methodologies, systems, and applications, and it is expanding into diverse computing paradigms such as perceptual intelligence, cognitive intelligence, autonomous intelligence, and human-computer fusion intelligence. This paper introduces the concept and main features of intelligent computing and describes trends in standardization for intelligent computing within the ISO/IEC JTC 1, focusing on the technical trend report on intelligent computing that is currently under development within ISO/ IEC JTC 1/AG 2.

• 한국HCI학회:학술대회논문집
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• 한국HCI학회 2008년도 학술대회 3부
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• pp.224-224
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• 2008

Recent advances in model acquisition, computer-aided design, and simulation technologies have resulted in massive databases of complex geometric data occupying multiple gigabytes and even terabytes. In various graphics/geometric applications, the major performance bottleneck is typically in accessing these massive geometric data due to the high complexity of such massive geometric data sets. However, there has been a consistent lower growth rate of data access speed compared to that of computational processing speed. Moreover, recent multi-core architectures aggravate this phenomenon. Therefore, it is expected that the current architecture improvement does not offer the solution to the problem of dealing with ever growing massive geometric data, especially in the case of using commodity hardware. In this tutorial, I will focus on two orthogonal approaches--multi-resolution and cache-coherent layout techniques--to design scalable graphics/geometric algorithms. First, I will discuss multi-resolution techniques that reduce the amount of data necessary for performing geometric methods within an error bound. Second, I will explain cache-coherent layouts that improve the cache utilization of runtime geometric applications. I have applied these two techniques into rendering, collision detection, and iso-surface extractions and, thereby, have been able to achieve significant performance improvement. I will show live demonstrations of view-dependent rendering and collision detection between massive models consisting of tens of millions of triangles on a laptop during the talk.