• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.106-113
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• 2017

In this paper, we propose a suitable network topology for the Ethernet based Train Communication Network (TCN) for control system in a autonomous multi-articulated vehicle. We propose a network topology considering the structural constraints such as the number of cables and ports, and the performance constraints such as network response time and maximum throughput. We compare the network performances of star topology and daisy chain topology as well as hybrid topology, which is proposed in previous studies and a compromise between daisy chain and star topology. Here, the appropriate number of nodes in a group is obtained for the configuration of the hybrid topology. We first derive estimates of the network performance through simulation with different topologies, and then, implement the network by connecting the actual devices with each network topology. The performance of each topology is measured using various network performance measurement programs and the superiority of the proposed topology is described through comparison.

• Journal of IKEEE
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• v.25 no.2
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• pp.315-321
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• 2021

In this paper, we have developed the multiple channel measurement system for IC Socket Test. The one can test the current-voltage measurements for pitting the several device specification, which analyze the thin current from several ㎂ to 5A with very low resistor mΩ. The increasement of the IC socket channel with lead pitch under 0.25 mm be need to perform several functions, concurrently. The system to perform these functions be designed to integrate several SMU(source measure unit) on board. So, we can reduce the 2 minutes test time per channel point to 40 sec, with daisy chain test method. Using by graphic interface, I-V curve mode and data logging technologies, we can implement the test flow methods and can make economies the time and cost.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.5C
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• pp.429-436
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• 2012

In this paper, an RFID system for the automatic preparation system of positron emission tomography (PET) radiopharmaceuticals is developed. Since the preparation system uses radioactive isotope, the preparation system is generally placed in lead-shielded hot-cell. Disposable cassettes including tubes and valves are used in the preparation system, since they are easily contaminated by radioactivity during preparation of radiopharmaceuticals. Currently, a system for preventing re-use of the cassette and managing the information about the preparation precess and result independently from the PC which control the preparation system is highly required for preventing danger from the radiation accident. Since RFID can store and re-write relatively large amount of information, it is suitable for the purpose. However, it is hard to read multiple cassettes' information using antennas installed on the metallic surfaces with current RFID systems. For the problem, we improve RFID system in two directions. First, the interface of the RFID reader is changed then it is possible that multiple readers can be daisy-chained. Also, antenna is tuned while inserting in a metallic coated antenna case, then the effect from the metallic surface of the preparation system is minimized. The test result using the developed system shows that the developed RFID system can read multiple tags using the antennas which are attached on the metallic surface.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2007.04a
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• pp.115-127
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• 2007

[ ${\blacktriangleright$ ] Various Factors to affect TC Reliability of 4 array RES has been Investigated through Simulation Tool and Daisy Chain Board Test ${\blacktriangleright$ Solder Joint Crack Mechanism of 4 array RES has been Examined Also, It has been Examined Thoroughly What Influence Each Factors gibes to TC Reliability and Why Those Factors gives an Influence to it ${\blacktriangleright$ BGA Type RES is Suggested to Improve TC Reliability (Patented) ${\blacktriangleright$ Through this Study, Best Design Parameter has been Optimized to Increase TC Reliability of 4 Array RES

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.72-75
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• 2003

솔더의 상호확산을 이용한 저온 칩 접합을 구현하기 위하여 $117^{\circ}C$의 공정 온도를 가지는 In과 Sn 솔더패드를 $25\;mm^2$의 접합면적에 형성하고 두 솔더의 융점 보다 낮은 온도인 $120^{\circ}C$에서 접합을 시행하였다. 30초의 반응시간에서도 접합이 이루어 졌으며 반응시간이 지남에 따라 두 솔더가 반응하여 혼합상을 형성하였다. 솔더패드 접합에서 접합부는 낮은 접속저항과 높은 접속강도를 가짐을 확인할 수 있었다. $40\;{\mu}m$의 극미세피치의 In, Sn 솔더 범프를 형성하여 접합부를 형성하였으며 daisy chain을 형성한 접합부를 이용하여 평균 $65\;m\Omega/bump$ 저항값을 얻을 수 있었다. 상온에서 시효후 $54\%$의 접속저항이 감소함을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Journal of Applied Reliability
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• v.13 no.2
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• pp.109-116
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• 2013

The solder is any of various fusible alloys, usually tin and lead, used to join metallic parts that provide the contact between the chip package and the printed circuit board. Solder plays an important role of electrical signals to communicate between the two components. In this study, two kinds of Ag-free solder as sample is made to conduct the thermal shock test and the high humidity temperature test. Low resistance is measured to estimate crack size of solder, using daisy chain. The low speed shear test is also performed to analyze strength of solder. The appropriate degradation model is estimated using the result data. Depending on the composition of solder, lifetime estimation is conducted by adopted degradation model. The lifetime estimated two kinds of Ag-free solder is compared with expected lifetime of Sn-Ag-Cu solder. The result is that both Ag-free composition are more reliable than Sn-Ag-Cu solder.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.61-68
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• 2002

Thermal shock testing was used to evaluate reliability that appeared in the solder joints of electronic devices when they were subjected to thermal cycling. Recently, mobile devices have come smaller and multi-functional, with the increasing need for high-density packaging, BGA or CSP has become the main trend for surface mounting technology, and therefore mechanical stress life for solder joints in BGA/CSP type packages has required. Reliability of BGA/CSP solder joints was evaluated with electric resistivity change of daisy chain pattern and stress-strain curve measured using strain gage attached on the surface of PCB under mechanical impact loading. In this report, applications of PCB Universal Testing Machine we have developed and experimental datum of SONY estimating dynamic behavior of mechanical stress in BGA/CSP solder joints are introduced.

• Korean Journal of Metals and Materials
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• v.46 no.2
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• pp.80-87
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• 2008

Many researches related to the reliability of Pb-free solder joints with PCB (printed circuit board) surface finish under thermal or vibration stresses are in progress, because the electronics is operating in hash environment. Therefore, it is necessary to assess Pb-free solder joints life with PCB surface finish under thermal and mechanical stresses. We have investigated 4-points bending fatigue lifetime of Pb-free solder joints with OSP (organic solderability preservative) and ENIG (electroless nickel and immersion gold) surface finish. To predict the bending fatigue life of Sn-3.0Ag-0.5Cu solder joints, we use the test coupons mounted 192 BGA (ball grid array) package to be added the thermal stress by conducting thermal shock test, 500, 1,000, 1,500 and 2,000 cycles, respectively. An 4-point bending test is performed in force controlling mode. It is considered that as a failure when the resistance of daisy-chain circuit of test coupons reaches more than $1,000{\Omega}$. Finally, we obtained the solder joints fatigue life with OSP and ENIG surface finish using by Weibull probability distribution.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.261-278
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• 2003

Concepts.Wafer-Level Chip-Scale Concept with Handling Substrate.Low Accuracy Placement Layout with Isolation Trench.Possible Pitch of Interconnections down to $10{\mu}{\textrm}{m}$ (Sn-Grains).Wafer-to-Wafer Equipment Adjustment Accuracy meets this Request of Alignment Accuracy (+/-1.5 ${\mu}{\textrm}{m}$).Adjustment Accuracy of High-Speed Chip-to-Wafer Placement Equipment starts to meet this request.Face-to-Face Modular / SLID with Flipped Device Orientation.interchip Via / SLID with Non-Flipped Orientation SLID Technology Features.Demonstration with Copper / Tin-Alloy (SLID) and W-InterChip Vias (ICV).Combination of reliable processes for advanced concept - Filling of vias with W as standard wafer process sequence.No plug filling on stack level necessary.Simultanious formation of electrical and mechanical connection.No need for underfiller: large area contacts replace underfiller.Cu / Sn SLID layers $\leq$ $10{\mu}{\textrm}{m}$ in total are possible Electrical Results.Measurements of Three Layer Stacks on Daisy Chains with 240 Elements.2.5 Ohms per Chain Element.Contribution of Soldering Metal only in the Range of Milliohms.Soldering Contact Resistance ($0.43\Omega$) dominated by Contact Resistance of Barrier and Seed Layer.Tungsten Pin Contribution in the Range of 1 Ohm