• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.5
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• pp.265-272
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• 2013

This paper addresses a control allocation method for fault-tolerant control by redistributing redundant control surfaces. The proposed method is based on a classical daisy chain approach for the compensation of faulty actuators. The existing daisy chain method calculates a desired moment according to a number of actuator groups. However, this method has a significant limitation; that is, any faulty actuator belonging to the last actuator group cannot be compensated, since there is no more redundant actuator group that can be used to generate the required moments. In this paper, a modified daisy chain method is proposed to overcome this problem. Using the proposed method, the order of actuator groups is readjusted so that actuator groups containing any faulty actuator are always placed in an upper group instead of the last one. A set of simulation results with an F-18 HARV aircraft demonstrate that the proposed method can achieve better performance than the existing daisy chain method.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.479-484
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• 2016

In this paper, a design of DC level shifter transmitting and receiving control and data signal which have various DC level through daisy chain interface between master IC and slave is introduced in the cell voltage monitoring (CVM). Circuit designed with a latch structure have a function to operate in high speed and for output of variable DC level through transmission gate. As a result of the simulation and the measurement, it was confirmed that control and data signal could be transferred according to the change of DC level from 0V to 30V. Delay time was measured about 170ns. but, it was considered as a negligible tolerance due to a parasitic capacitance of measuring probe and test board.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.3
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• pp.177-181
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• 2013

As smart devices and OS with communication capabilities based latest NFC (Near Field Communication) have been spreaded, many applications with using existing RFID are being replaced to NFC. Smart NFC technology and existing services and devices can be easily combined convergence and advantage of smart phones, such as authentication and billing, medical care, the creation of a new paradigm of Network Communication are to be expected. By developing H/W, S/W of the Smart NFC Security Authenticator(SNSA), satisfying with wireless communication test results within accepted reference value, analyzing and testing the impact of topology, the signal performance of Daisy Chain Topology was much better than Star Topology's.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.149-152
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• 2011

A Multi-Vision needs an image adjust of each product to make the same picture quality for all products when it's installed. Owing to this reason need individual control. This document request indivisual control method for each product with the Remote controller. To realize this method need make Set ID and Picture ID on the UI and need daisy chain of cable to connect Remocon code(IR Signal) In to Out, After allocation the Set ID for each product. Picture ID of the product which want to change picture quality make equal to Set ID. And the product which is same Set ID and Picture ID is only controlled through decoding of Remocon code to Scaler.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2747-2754
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• 2012

This thesis explains the development of multiple LCD system with the additional function to maximize the utilization of PC contents. The newly developed system is composed of host LCD and slave LCD. Host LCD decodes and outputs the image and voice of NTSC, PAL, SECAM signals. It also converts the decoded signals into LVDS signals before transmitting them to slave LCD stage. In addition, the installation of CF Memory and USB Memory helps display multi-media data. Unlike the host LCD, since not including the tuner and memory part, the slave LCD can't receive TV signals and play video signals. It only has the function to receive LVDS image signals and display on a LCD panel. This newly developed multi-LCD system has competitiveness in various aspects. With its simple structure, the failure rate, price and display power are relatively low due to its simplification of the control part. It has price and functional competitiveness as the product whose host LCD can control the entire slave LCD in terms of channel, volume, and video output.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.6
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• pp.20-26
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• 2001

In this paper, we design tunnel inner section displacement measurement system which is composed of potentiometer-type displacement sensors, microcontroller-based intelligent sensing head and host computer for the management system and acquisition data. Multiple node communication bus connects the intelligent sensing heads with the host computer. For safe and re1iab1e network operation we use daisy-chain configuration, termination resistor, fail-safe biasing circuit. For tole enhancement of system utilization, we use modbus protocol. The acquisition data are transmitted to host computer and managed by database. Several data request conditions and sorting conditions are provided by management software. The utilization of designed system is confirmed by experiment.

• ETRI Journal
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• v.35 no.6
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.27-34
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• 2016

In the train system, railway vehicles are connected in a line. Therefore, this feature should be considered in composing network topology in a train system. Besides, inter-car communication should be distinguished from in-car communication. As for the inter-car communication, the hybrid topology was proposed to use rather than the conventional ring, star, daisy-chain, and bus topologies. In the hybrid topology, a number of cars are bound to be a group. Then star topology is used for the communication in a group and daisy-chain topology is used for the communication between groups. Hybrid topology takes the virtue of both star and daisy-chain topologies. Hence it maintains communication speed with reducing the number of connecting cables between cars. Therefore, it is important to choose the number of cars in a group to obtain higher performance. In this paper, we focus on the optimization of hybrid topology for railway cars. We first assume that the size of data and the frequency of data production for each car is identical. We also assume that the importance for the maximum number of cables to connect cars is variable as well as the importance of the communication speed. Separated weights are granted to both importance and we derive the optimum number of cars in a group for various number of cars and weights.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.55-59
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• 2015

Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.