• Title/Summary/Keyword: DVB-S

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A Soft Demapping Method for 64-APSK in the DVB-S3 System (DVB-S3 시스템의 64-APSK 방식에 대한 연판정 비트 검출 기법)

  • Li, Guowen;Zhang, Meixiang;Kim, Sooyoung
    • Journal of Satellite, Information and Communications
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    • v.9 no.2
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    • pp.23-27
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    • 2014
  • In this paper, we propose a soft demapping method for 64-ary APSK in the DVB-S3 system. The proposed method in this paper uses the hard decision threshold (HDT) line for each constituent bit in a symbol, and calculates the soft bit information with the distance between the HDT line and the detected symbol. If the HDT lines are defined in a simple manner, the complexity to estimate soft information can be largely reduced compared with the maximum likelihood detection (MLD) which has an exponential complexity. By considering this, we first derive HDT lines for each constituent bit for a 64-APSK symbol, and propose a method to calculate soft bit information. We simulate the BER performance of the proposed scheme by using a turbo codes which requires soft-input-soft-output information, and compare it that of the MLD. The result show that the proposed scheme produces approximating performance to MLD with largely reduced complexity.

A 12b 100MS/s 1V 24mW 0.13um CMOS ADC for Low-Power Mobile Applications (저전력 모바일 응용을 위한 12비트 100MS/s 1V 24mW 0.13um CMOS A/D 변환기)

  • Park, Seung-Jae;Koo, Byeong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.8
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    • pp.56-63
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    • 2010
  • This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

Estimation of Physical Layer Scrambling Code Sequence of DVB-S2

  • Wu, Hao;Xie, Hui;Huang, Zhi-Tao;Zhou, Yi-Yu
    • ETRI Journal
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    • v.36 no.2
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    • pp.329-332
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    • 2014
  • In this letter, the problem of estimating the physical layer (PL) scrambling code sequence of DVB-S2 is studied. We present the first ever scheme to estimate the scrambling sequence. The scheme is based on hypothesis testing. By analyzing the PL scrambling process, we construct a new sequence equivalent to the scrambling sequence. We then use hypothesis testing to estimate the new sequence. The threshold for the hypothesis testing is also discussed. The experiment results show that the performance of our estimation scheme can work even under high BER.

Synchronization Schemes for SVC Signals in the Layered Modulation System (계층적 변조 시스템에서 SVC 신호의 동기화 방안)

  • Huynh, Tan-Bao;Kim, Seung-Chul;Sohn, Won
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2009.11a
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    • pp.97-100
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    • 2009
  • The paper describes synchronization schemes for scalable video coding signals over the DVB-S2 network. The MPEG-4 SVC signals include a base layer signal and an enhancement layer signal. They are packetized into MPEG-2 transport streams and transmitted on separate RF channels through the DVB-S2 system. The DVB-S2 receiver is required to synchronize each layer signal together to recover the full pictures. Some new schemes to synchronize two. layered SVC signals in MPEG-4 SVC decoder are proposed and analyzed.

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Study on the Link Analysis for Satellite Broadcasting Service Using Ka Band Transponders in the Korean Area

  • Yoon, Ki-Chang;Kim, Seung-Chul;Sohn, Won
    • Journal of Satellite, Information and Communications
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    • v.3 no.2
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    • pp.7-12
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    • 2008
  • The study discussed the link analysis for the Ka band satellite broadcasting service in Korea with respect to the transmission schemes based on the DVB-S2 standard. To analyze the effect of the rain fading to the link budget, we estimated the rain attenuation from the measured rainfall intensity in Korea. We analyzed the link budget for the Ka band transponders of Koreasat-3, and DirecTV BSS-99W, and showed the possible link availability with the DVB-S2 transmission schemes for each transponder. Based on the link analysis of the available satellites with the Ka band transponders, we suggested the required EIRP for the satellite which will be employed for the Ka band satellite broadcasting service in Korea.

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Hardware Design of SNR estimator for DVB-S2 terminal (DVB-S2 수신기를 위한 신호 대 잡음비 추정 하드웨어 설계)

  • Park, Eun-Woo;Yi, Jae-Ung;Kim, Soo-Seong;Im, Chae-Yong;Yeo, Sung-Moon;Kim, Soo-Young
    • Proceedings of the IEEK Conference
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    • 2007.07a
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    • pp.47-48
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    • 2007
  • This paper presents an efficient and simple hardware design of signal to noise ratio (SNR) estimator for DVB-S2 system. The estimator investigates the distribution of the received symbols by simply using two comparators and a counter, and calculates the address of an LUT where the corresponding SNR value is located. In this paper, we demonstrate the functional and timing simulation results of the FPGA implementation of proposed structure.

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Design Methodology of LDPC Codes based on Partial Parallel Algorithm (부분병렬 알고리즘 기반의 LDPC 부호 구현 방안)

  • Jung, Ji-Won
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.4
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    • pp.278-285
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    • 2011
  • This paper makes an analysis of the encoding structure and the decoding algorithm proposed by the DVB-S2 specification. The methods of implementing the LDPC decoder are fully serial decoder, the partially parallel decoder and the fully parallel decoder. The partial parallel scheme is the efficient selection to achieve appropriate trade-offs between hardware complexity and decoding speed. Therefore, this paper proposed an efficient memory structure for check node update block, bit node update block, and LLR memory.

Efficient Channel Estimation and Packet Scheduling Scheme for DVB-S2 ACM Systems (DVB-S2 ACM 시스템을 위한 효율적인 채널 예측 및 패킷 스케줄링 기법)

  • Kang, Dong-Bae;Park, Man-Kyu;Chang, Dae-Ig;Oh, Deock-Gil
    • Journal of Satellite, Information and Communications
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    • v.7 no.1
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    • pp.65-74
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    • 2012
  • The QoS guarantee for the forward link in satellite communication networks is very important because there are a variety of packets with multiplexing. Especially, the packets are processed depending on the available bandwidth in satellite network changing the wireless channel state in accordance with weather condition. The DVB-S2 increases the transmission efficiency by applying the adaptive coding and modulation (ACM) techniques as a countermeasure of rain attenuations. However, the channel estimation algorithm is required to support the ACM techniques that select the MODCOD values depending on the feedback data transmitted by RCSTs(Return Channel via Satellite Terminal) because satellite communication networks have a long propagation delay. In this paper, we proposed the channel estimation algorithm using rain attenuation values and reference data and the packet scheduling scheme to support the QoS and fairness. As a result of performance evaluation, we showed that proposed algorithm exactly predicts the channel conditions and supports bandwidth fairness to the individual RCST and guarantees QoS for user traffics.

Implementation of FFT on Massively Parallel GPU for DVB-T Receiver (DVB-T 수신기를 위한 대규모 병렬처리 GPU 기반의 FFT 구현)

  • Lee, Kyu Hyung;Heo, Seo Weon
    • Journal of Broadcast Engineering
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    • v.18 no.2
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    • pp.204-214
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    • 2013
  • Recently various research have been conducted relating to the implementation of signal processing or communication system by software using the massively parallel processing capability of the GPU. In this work, we focus on reducing software simulation time of 2K/8K FFT in DVB-T by using GPU. we estimate the processing time of the DVB-T system, which is one of the standards for DTV transmission, by CPU. Then we implement the FFT processing by the software using the NVIDIA's massively parallel GPU processor. In this paper we apply stream process method to reduce the overhead for data transfer between CPU and GPU, coalescing method to reduce the global memory access time and data structure design method to maximize the shared memory usage. The results show that our proposed method is approximately 20~30 times as fast as the CPU based FFT processor, and approximately 1.8 times as fast as the CUFFT library (version 2.1) which is provided by the NVIDIA when applied to the DVB-T 2K/8K mode FFT.

A Design of the Demapper Using Channel State Information for COFDM Demodulator (COFDM 복조기에서의 채널상태정보를 이용한 디매퍼의 설계)

  • Kang, Kyung-Jin;Lee, Weon-Cheol
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.10
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    • pp.21-29
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    • 1999
  • This paper is concerning about the demapping method using the pilots inserted in transmitter in COFDM(Coded Orthogonal Frequency Division Multiplexing) demodulator which is the standard transmission method of terrestrial digital TV system in Europe(DVB-T). We have presented a simple and efficient method of CSI(Channel State Information) generation and demapping method using CSI. The CSI was derived from the pilot carriers inserted with comb-type among the received active carriers, which is defined as a SNR. From the simulation results for the 3 different constellations of the receiver, we could confirm that the system performance comparing with conventional soft decision method has been improved under DVB-T standard Rayleigh and Ricean fading channel.

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