• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.8
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• pp.748-756
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• 2015

In this paper, we developed a miniaturized real time video compression system satisfying the military environment using ADV212 and FPGA. We present an efficient hardware design scheme for the weight reduction of the device and also a software solution to deal with noisy image signals. Experimental results show that the frame delay is reduced by a factor of 2 or 3 and the device's weight is decreased by a factor of 6 to 7. In order to prove the reliability for the military usage of this development, we examine the environmental test (MIL-STD-810G) and EMI test (MIL-STD-461F). Experimental results show that the developed system satisfies the requirements.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.9
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• pp.4389-4411
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• 2018

High dynamic range (HDR) images are becoming pervasive due to capturing or rendering of a wider range of luminance, but their special display equipment is difficult to be popularized because of high cost and technological problem. Thus, HDR images must be adapted to the conventional display devices by applying tone mapping (TM) operation, which puts forward higher requirements for intellectual property protection of HDR images. As the robustness presents regional diversity in the low dynamic range (LDR) watermarked image after TM, which is different from the traditional watermarking technologies, a concept of watermarking activity is defined and used to distinguish the essential distinction of watermarking between LDR image and HDR image in this paper. Then, a novel robust HDR image watermarking algorithm is proposed against TM operations. Firstly, based on the hybrid processing of redundant discrete wavelet transform and singular value decomposition, the watermark is embedded by modifying the structure information of the HDR image. Distinguished from LDR image watermarking, the high embedding strength can cause more obvious distortion in the high brightness regions of HDR image than the low brightness regions. Thus, a perceptual brightness mask with low complexity is designed to improve the imperceptibility further. Experimental results show that the proposed algorithm is robust to the existing TM operations, with taking into account the imperceptibility and embedded capacity, which is superior to the current state-of-art HDR image watermarking algorithms.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1203-1204
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• 2006

Recently, utility network is getting more and more complicated and huge. In addition to, demands of power conversion devices which have non-linear switching devices are getting more and more increased. Consequently, according to the non-linear power semiconductor devices, current harmonics are unavoidable. Those current harmonics flow back to utility network and become one of the reasons which make the voltage distortion. On the other hands, voltage sag from sudden increasing loads is also one of the terrible problems inside of utility network. In order to compensate the current harmonics and voltage sag problem, AF(Active Filter) systems could be a good solution method and SMES(Superconducting Magnetic Energy Storage) system is a very good promising source due to the high response time of charge and discharge. Therefore, the combined system of AF and SMES is a wonderful device to compensate both harmonics current and voltage sag. However, unfortunately SMES needs a superconducting magnetic coil. Because of the introduction of superconducting magnetic coil, quench problem caused by unexpected reasons is always existed. In case of discharge operation, quench is a significantly harmful factor according as it decreases the energy capacity of SMES. Therefore, this paper presents a decision method of the specification of the AF-SMES system considering internal fault condition. Especially, authors analyzed the change of the original energy capacity of SMES regarding to the size of resistance caused by quench of superconducting magnetic coil. Finally, based on this simulation, authors manufactured actual Active Filter System using DSP.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.6
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• pp.517-525
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• 2015

A grid connected inverter must be operated as the main electricity source under an isolated condition caused by the grid problem. Conventionally, the dual loop controller is used for the grid inverter, and the controller is used for control under the stand-alone mode. Generally, the PI(Proportional - Integral) controller is highly efficient under a synchronous reference frame, and stable control can be available. However, in this synchronous frame-based control, high-quality DSP is required because many sinusoidal calculations are necessary. When the PI control is conducted under a stationary frame, the controller constructions are made simple so that they work even with a low-price micro controller. However, given the characteristics of the PI controller, it should be designed with the phase of reference voltage considered. Otherwise, the phase delay of the output voltage can occur. Although the current controller also has a higher bandwidth than the voltage controller, distortion of the voltage is difficult to avoid only by the rapid response of the PI controller, as a sudden load change can occur in the nonlinear load. In this study, a new control method that solves the voltage controller bandwidth problem and rapidly copes with it even in the nonlinear load situation is proposed. The validity of the proposed method is proved by simulation and experimental results.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.168-180
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• 2018

In order to achieve the high quality output voltage of single-phase voltage source inverters, in this paper an Adaptive Complementary Sliding Mode Control (ACSMC) is proposed. Firstly, the dynamics model of the single-phase inverter with lumped uncertainty including parameter variations and external disturbances is derived. Then, the conventional Sliding Mode Control (SMC) and Complementary Sliding Mode Control (CSMC) are introduced separately. However, when system parameters vary or external disturbance occurs, the controlling performance such as tracking error, response speed et al. always could not satisfy the requirements based on the SMC and CSMC methods. Consequently, an ACSMC is developed. The ACSMC is composed of a CSMC term, a compensating control term and a filter parameters estimator. The compensating control term is applied to compensate for the system uncertainties, the filter parameters estimator is used for on-line LC parameter estimation by the proposed adaptive law. The adaptive law is derived using the Lyapunov theorem to guarantee the closed-loop stability. In order to decrease the control system cost, an inductor current estimator is developed. Finally, the effectiveness of the proposed controller is validated through Matlab/Simulink and experiments on a prototype single-phase inverter test bed with a TMS320LF28335 DSP. The simulation and experimental results show that compared to the conventional SMC and CSMC, the proposed ACSMC control strategy achieves more excellent performance such as fast transient response, small steady-state error, and low total harmonic distortion no matter under load step change, nonlinear load with inductor parameter variation or external disturbance.

• Journal of Power Electronics
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• v.3 no.4
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• pp.249-258
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• 2003

This paper presents a high-efficient and cost effective three-phase AC/DC-DC/AC power conversion system with a single two-switch type active Auxiliary Resonant DC Link (ARDCL) snubber circuit, which can minimize the total power dissipation. The active ARDCL snubber circuit is proposed in this paper and its unique features are described. Its operation principle in steady-state is discussed for the three phase AC/DC-DC/AC converter, which is composed of PWM rectifier as power factor correction (PFC) converter, sinewave PWM inverter. In the presented power converter system not only three-phase AC/DC PWM rectifier but also three-phase DC/AC inverter can achieve the stable ZVS commutation for all the power semiconductor devices. It is proved that the proposed three-phase AC/DC-DC/AC converter system is more effective and acceptable than the previous from the cost viewpoint and high efficient consideration. In addition, the proposed two-switch type active auxiliary ARDCL snubber circuit can reduce the peak value of the resonant inductor injection current in order to maximize total system actual efficiency by using the improved DSP based control scheme. Moreover the proposed active auxiliary two-switch ARDCL snubber circuit has the merit so that there is no need to use any sensing devices to detect the voltage and current in the ARDCL sunbber circuit for realizing soft-switching operation. This three-phase AC/DC-DC/AC converter system developed for UPS can achieve the 1.8% higher efficiency and 20dB lower conduction noise than those of the conventional three-phase hard-switching PWM AC/DC-DC/AC converter system. It is proved that actual efficiency of the proposed three-phase AC/DC-DC/AC converter system operating under a condition of soft switching is 88.7% under 10kw output power.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.1
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• pp.89-97
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• 2007

This paper describes a load simulator with power recovery capability, which is based on the voltage source converter-inverter set. The load simulator can save the electric energy that should be consumed to test the operation and performance of the power quality compensator and the power equipment. The load simulator consists of a converter-inverter set with a DSP controller for system control and PWM pulse generation. The converter operates as a universal load to model the linear load and the non-linear load, while the inverter feed the energy back to the power source with harmonic compensation. the performance of proposed load simulator was analyzed with scaled-model experiment, interconnected with the active power filter. The experimental results confirms that the proposed load simulator can be utilized to test the performance of active power filter.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.401-408
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• 2012

A simple on-line elimination strategy of the dead time and inverter nonlinearity using the current slope information is presented for a PWM inverter-fed IPMSM (Interior Permanent Magnet Synchronous Motor) drive. In a PWM inverter-fed IPMSM drive, a dead time is inserted to prevent a breakdown of switching device. This distorts the inverter output voltage, resulting in a current distortion and torque ripple. In addition to the dead time, inverter nonlinearity exists in switching devices of the PWM inverter, which is generally dependent on operating conditions such as the temperature, DC link voltage, and current. The proposed scheme is based on the fact that the d-axis current ripple is mainly caused by the dead time and inverter nonlinearity. To eliminate such an influence, the current slope information is determined. The obtained current slope information is processed by the PI controller to estimate the disturbance caused by the dead time and inverter nonlinearity. The overall system is implemented using DSP TMS320F28335 and the validity of the proposed algorithm is verified through the simulation and experiments. Without requiring any additional hardware, the proposed scheme can effectively eliminate the dead time and inverter nonlinearity even in the presence of the parameter uncertainty.