• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.797-802
• /
• 2020

In this paper, we presents the design and implementation results of the FFT processor, which supports 4096 points of operation with less memory by sharing several memory used in the base-4 systolic array FFT processor into one memory. Sharing memory provides the advantage of reducing the area, and also simplifies the flow of data as I/O of the data progresses in one memory. The presented FFT processor was implemented and verified on the FPGA device. The implementation resulted in 51,855 CLB LUTs, 29,712 CLB registers, 8 block RAM tiles and 450 DSPs, and confirmed that the memory area could be reduced by 65% compared to the existing base-4 systolic array structure.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.46 no.4
• /
• pp.94-101
• /
• 2009

In this paper, we propose design of hardware based on a high speed digital signal processor (DSP) and a field programmable gate array (FPGA) for real-time suppression of fixed pattern noise (FPN) using hardware neural networks (HNN) in cooled infrared focal plane array (IRFPA) imaging system FPN appears a limited operation by temperature in observable images which applies to non-uniformity correction for infrared detector. These have very important problems because it happen serious problem for other applications as well as degradation for image quality in our system Signal processing architecture for our system operates reference gain and offset values using three tables for low, normal, and high temperatures. Proposed method creates virtual tables to separate for overlapping region in three offset tables. We also choose an optimum tenn of temperature which controls weighted values of HNN using mean values of pixels in three regions. This operates gain and offset tables for low, normal, and high temperatures from mean values of pixels and it recursively don't have to do an offset compensation in operation of our system Based on experimental results, proposed method showed improved quality of image which suppressed FPN by change of temperature distribution from an observational image in real-time system.

• Publications of The Korean Astronomical Society
• /
• v.21 no.2
• /
• pp.67-74
• /
• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

• International Journal of Control, Automation, and Systems
• /
• v.1 no.2
• /
• pp.252-256
• /
• 2003

A biped robot should be designed to be an effective mechanical structure and have smaller hardware system if it is to be a stand-alone structure. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU, and FPGA as the motor controller. By using FPGA, more flexible hardware system has been achieved, and more compact and simple controller has been designed.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.242-243
• /
• 2017

기존 Digital Signal Processor (DSP)를 사용하여 높은 동작 주파수의 LLC 공진형 컨버터를 구동하는 경우 낮은 동작 주파수 분해능과 계산 속도에 의해 출력 전압 제어성능과 동특성에 한계가 생긴다. 이를 해결하기 위해 기존의 분해능 및 계산 속도 부족에 의한 영향을 분석하고 Field Programmable Gate Array (FPGA)를 설계하여 높은 동작 주파수 분해능 및 동특성을 얻고자 제안한다. FPGA를 이용한 성능향상을 DSP (TI - TMS 38335)와 FPGA (Xilinx XC7A100T)를 사용하여 비교 분석하고자 한다.

• Investigative Magnetic Resonance Imaging
• /
• v.7 no.1
• /
• pp.12-21
• /
• 2003

Purpose : In order to overcome limitations in the existing conventional spectrometer, a new spectrometer with advanced functionalities is designed and implemented. Materials and Methods : We designed a spectrometer using the TMS320C6701 DSP capable of 1 giga floating point operations per second (GFLOPS). The spectrometer can generate continuously varying complicate gradient waveforms by real-time calculation, and select image plane interactively. The designed spectrometer is composed of two parts: one is DSP-based digital control part, and the other is analog part generating gradient and RF waveforms, and performing demodulation of the received RF signal. Each recover board can measure 4 channel FID signals simultaneously for parallel imaging, and provides fast reconstruction using the high speed DSP. Results : The developed spectrometer was installed on a 1.5 Tesla whole body MRI system, and performance was tested by various methods. The accurate phase control required in digital modulation and demodulation was tested, and multi-channel acquisition was examined with phase-array coil imaging. Superior image quality is obtained by the developed spectrometer compared to existing commercial spectrometer especially in the fast spin echo images. Conclusion : Interactive control of the selection planes and real-time generation of gradient waveforms are important functions required for advanced imaging such as spiral scan cardiac imaging. Multi-channel acquisition is also highly demanding for parallel imaging. In this paper a spectrometer having such functionalities is designed and developed using the TMS320C6701 DSP having 1 GFLOPS computational power. Accurate phase control was achieved by the digital modulation and demodulation techniques. Superior image qualities are obtained by the developed spectrometer for various imaging techniques including FSE, GE, and angiography compared to those obtained by the existing commercial spectrometer.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.3
• /
• pp.198-206
• /
• 2011

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

• 제어로봇시스템학회:학술대회논문집
• /
• 2004.08a
• /
• pp.1565-1567
• /
• 2004

Various defects are found in FPD (Flat Panel Display) manufacturing process. So detecting these defects early and reprocessing them is an important factor that reduces the cost of production. In this paper, the bare glass inspection system for the FPD which is the early process inspection system in the FPD manufacturing process is designed and implemented using the high performance and accuracy CCD line scan camera. For the preprocessing of the high speed line image data, the Image Processing Part (IPP) is designed and implemented using high performance DSP (Digital signal Processor), FIFO (First in First out), FPGA (Field Programmable Gate Array) and the Data Management and System Control part are implemented using ARM (Advanced RISC Machine) processor to control many IPP and cameras and to provide remote users with processed data. For evaluating implemented system, experiment environment which has an area camera for reviewing and moving shelf is made.

• Proceedings of the KOSOMBE Conference
• /
• v.1995 no.11
• /
• pp.278-281
• /
• 1995

In this paper, we have developed EEG (electroencephalography) analyzer for monitoring the condition of brain in neurological surgery. This system is composed of EEG amplifier. personal-computer and BSP (Digital Signal Processor). By parallel processing of DSP, this system can analysis the power spectral density change of EEG in real-time and display the CSA(Compressed Spectral Array) and CDSA(Color Density Spectral array) of EEG. This system was tested by real EEG and showed the change of EEG.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.2
• /
• pp.29-35
• /
• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.