• The Journal of the Acoustical Society of Korea
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• v.19 no.7
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• pp.42-47
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• 2000

This paper describes a real-time implementation of a GSM-EFR (Global System for Mobil communications Enhanced Full Rate) speech coder using OakDSP core; a 16bit fixed-point Digital Signal Processor (DSP) by DSP Group, Inc. The real-time implemented speech coder required about 24MIPS for computation and 7.06K words and 12.19K words for code and data memory, respectively. The implemented GSM-EFR speech coder passes all of test vectors provided by ETSI (European Telecommunication Standard Institute), and perceptual speech quality measurement using MNB algorithm shows that the quality of the GSM-EFR speech coder is similar to the one of 32kbps ADPCM. The real-time implemented GSM-EFR speech coder which is the highest bit-rate mode of the GSM-AMR speech coder will be used as the basic structure of the GSM-AMR speech coder which is embedded in MODEM ASIC of IMT2000 asynchronous mode mobile station.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.372-375
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• 2001

본 논문에서는 고속데이터 전송을 위한 CDMA 모뎀를 구현하였다. 데이터율 1Mbps의 트래픽 5채널에 직교부호를 곱하여 채널을 구분한 후 하나의 채널로 처리하였다. I,Q로 입력된 신호는 복소 곱셈기에서 칩 레이트 8Mcps로 OCQPSK(또는 HPSK) 변조하였다. 복조기는 I,Q의 신호를 역확산한 후 직교부호를 다시 곱하여 각 채널의 데이터를 분리한다. 변복조기의 구현은 클럭 속도 167MHz의 부동 소수점형 프로세서인 TI사의 TMS320C6701 DSP(Digital Signal Processor)를 사용하었고, long code 및 I,Q 채널 PN 코드는 IMT-2000 동기방식과 비동기방식의 규격에 정의된 2가지의 PN코드 발생기를 모두 구현하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.9-12
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• 2001

본 논문에서는 유럽 통신 표준화기구인 ETSI 의 SMGll에서 채택된 GSM Full Rate(FR) 보코더 알고리wma[1]을 Teak DSP Core를 이용하여 실시간 구현하였다. GSM FR 보코더는 유럽에서 사용하는 통신 시스템인 GSM 의 full-rate Traffic Channel(TCH)의 표준 코덱[2]으로서 GSM HR, GSM EFR GSM AMR과 더불어 모뎀칩 내에 장착되는 필수적인 음성 서비스이다. 구현된 GSM FR는 13.05kbps의 비트율을 가지고 있으며, 인코더와 디코더 기능 외에 voice activity detection(VAD)[3]블록과 DTX[4]블록 등의 부가 기능도 구현되어 있다. 구현에 사용된 Teak[5]는 DSP Group 의 16bit고정 소수점 DSP core로서 최대 140MIPS 의 성능을 낼 수 있고 400bits ALU 와 두개의 MAC 이 장착되어 있어 음성 및 채널 부호화기의 실시간 처리에 최적화 되어있다. 구현된 GSM FR 은 인코더와 디코더 부분이 각각 약 235 MIPS 및 1.19MIPS 의 복잡도를 나타내며, 사용된 메모리는 프로그램 ROM 3.9K words, 데이터 ROM(table) 396 words 및 RAM 932words이다.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.984-990
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• 2010

In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2003.05a
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• pp.75-80
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• 2003

The Ministry of Maritime Affairs ＆ Fisheries have plaining the advancing fishery information integrated system for the fishing present condition, marine resource administration and applicability considering. The fishery information communication system is build up to the raw date ＆ process-network-content. The communication system must be small size, low cost and adapted SSB transceiver, that is using fishery shipping. In this paper We present digital data communication network to exchange information for fishery and safety between fishing ship and coast station in cheeper communication free using SSB(Single Side Band) in HF(High Frequency) band.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.249-251
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• 1994

This paper introduces an implementation of high performance voltage source inverter system based on 16bit micro-processor and DSP for the application to modem rolling stock traction system. In contrast with other industry oriented inverter system, this system requires precise control action complying with various load condition and high overload capability. An asynchronous PWM generation and 3' pulse mode technology are adopted in order to improve compliant starting torque characteristics at starting phase and soft backward-forward starting motion.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.1
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• pp.148-156
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• 2007

This paper explains stocker system that is operated in the long distance and linear area. The power system of stocker system uses Contactless Power Supply(CPS) to reduce problems of particle generation. The circuit configuration of CPS is simplified than the conventional ones, and the prototype is designed for commercial product. To transfer output data(information) from crane(secondary vehicle system) of the CPS to Primary system optical modem and TMS320F243(DSP, TI) are used between primary and secondary. power system are used, and the output voltage is controlled by operating frequency modulation. This paper is applied to stocker system controlled as one to one communication between the moving part(secondary system) and fixed part(primary system) of crane using optical modem. The study makes one to multi communication between fixed part and moving part for the purpose of multi crane operation of stocker system and must be done in the future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.387-393
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• 2008

In this paper, we present an SDR (Software Defined Radio) handset modem platform which supports communication systems such as HSDPA (High Speed Downlink Packet Access), and WiBro (Wireless Broadband Portable Internet). The proposed SDR platform employs DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), and microprocessors in such a way that the various communication functions like HSDPA and WiBro can be programmed and downloaded to the hardware platform. The proposed SDR platform can be used for functional verification of the physical layers of the mobile handset system in the mobile communication network. We first demonstrate the receiving structure of the physical layer of the HSDPA and WiBro system. Then, the hardware implementation of the proposed SDR platform is shown with functions and optimized signal flows required at each mode. Finally, the link performance of each mode operating on the proposed SDR platform is presented through the internal loopback tests with the test vectors. The experimental performance has been compared with the computer simulation results.