• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.5
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• pp.336-342
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• 2017

Recently, there has been an increasing need for underwater communication systems to monitor ocean environments and prevent marine disasters, as well as to secure ocean resources. Most underwater communication systems adopted acoustic communication with a consideration of attenuation, absorption, and scattering in conductive sea water, and developed fully digital modems based on processors. In this study, a digital up converter (DUC) and a digital down converter (DDC) was developed for an underwater basestation based on underwater acoustic communication systems. Because one of the most important issues in underwater acoustic communication systems is low power consumption due to environmental problems, this study developed a specific hardware module for DUC and DDC. It supported four links of underwater acoustic communication systems and converted the sampling rate and frequency. The systemwas designed and verified using Verilog-HDL in ModelSim environment with the test data generated from baseband layer parts for an underwater base station.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.6
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• pp.839-847
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• 2011

Instrumentation & Control(I&C) System in NPP(Nuclear Power Plant) plays a important role as the brain of human being, it performs protecting, controling and monitoring safety operation of NPP. Recently, the I&C system is digitalized as digital technology such as PLC, DSP, FPGA. The different aspect of digital system which use digital communication to analog system is that it has potential vulnerability to cyber threat in nature. Possibility that digital I&C system is defected by cyber attack is increasing day by day. The result of cyber attack can be adverse effect to safety function in NPP. Therefore, I&C system required cyber security counter-measures that protect themselves from cyber threat efficiently and also cyber security design should be taken into consideration at concept stage in I&C system development process. In this study, we proposed the digital asset analysis method for cyber security assessment of I&C system design in NPP and we performed digital asset analysis of I&C system by using the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.387-393
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• 2008

In this paper, we present an SDR (Software Defined Radio) handset modem platform which supports communication systems such as HSDPA (High Speed Downlink Packet Access), and WiBro (Wireless Broadband Portable Internet). The proposed SDR platform employs DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), and microprocessors in such a way that the various communication functions like HSDPA and WiBro can be programmed and downloaded to the hardware platform. The proposed SDR platform can be used for functional verification of the physical layers of the mobile handset system in the mobile communication network. We first demonstrate the receiving structure of the physical layer of the HSDPA and WiBro system. Then, the hardware implementation of the proposed SDR platform is shown with functions and optimized signal flows required at each mode. Finally, the link performance of each mode operating on the proposed SDR platform is presented through the internal loopback tests with the test vectors. The experimental performance has been compared with the computer simulation results.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.66-74
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• 2008

Surveillance system using active tracking camera has no distance limitation of surveillance range compared to supersonic or sound sensors. However, complex motion tracking algorithm requires huge amount of computation. Compared to conventional methods using DSPs or embedded processors, this paper proposes and implements a novel motion tracker unit that detects and extracts motion information of moving objects by using picture difference of consecutive frames. The proposed motion tracker unit was implemented in FPGA with about 13,000 gates. It processes NTSC format video and was verified by embedding it into the active surveillance camera system. We also propose and implements a motion estimator unit linkable to video codec by embedding the proposed motion tracker unit into ready-made motion estimator unit. The implemented motion estimator unit is about 17,000 gates in $0.35{\mu}m$ process.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.202-208
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• 2001

A Switched Reluctance Motor(SRM) has double salient poles structure and the phase windings are wound in stator. SRM hase more simple structure that of other motor, thus manufacture cost is low, mechanically strong, reliable to a poor environment such as high temperature, and maintenance cost is low because of brushless. SRM needs position detector to get rotator position information for phase excitation and tachometer or encoder for constant speed operation. But, this paper doesn\`s use an encoder of high cost for velocity measurement of rotator. Instead of it, the algorithm for position detection and velocity estimation from simple slotted disk has been proposed and developed. To implement variable speed digital control system with velocity estimation algorithm, the TMS320F240-20MIPS fixed point arithmetic processor of TI corporation is used. The experimental results of the developing system are enable to control speed with wide range, not only single pulse, hard chopping mode and soft chopping, ut also variable speed control, and advance angle control.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.959-962
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• 2005

Servomotors are used as key components of automated system by performing accurate positioning, accurate speed regulation, and precise motion control in response to commands from computers and sensors. Especially linear brushless servomotors have numerous advantages over ball screws, timing belts, rack/pinion drives and friction drives compared with rotary servomotors. This paper proposes the estimation of unknown parameters from the linear brushless DC motor which is operated by sinusoidal commutation. The estimated parameters are used to tune the controller gain and disturbance observer. In order to agree with this purpose, Digital Signal Processor(TMS320F240), developed for implementation of a speed Field Oriented Control(FOC), adopted in this study. The processor playing an important role in controller has A/D converters, PWM generators, riched I/O port internally.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.934-937
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• 2010

In this paper, we did pursue the embodiment of a mouse pointing system which help the handicapped and people of not familiar with using electronics use electronic devices easily. Speech Recognition and 3-axis acceleration sensors in conjunction with a headset, a new mouse pointing system is constructed. We used speaker dependent system module which are generating the BCD code by recognizing human voices because it has high recognition rate rather than speaker independent system. Head-set mouse system is organized by 3-axis accelerometer, sound recognition module and TMS320F2812 processor. The main controller, TMS320F2812 DSP-processor is communicated with main computer by using SCI communications. The system is operated by Visual Basic in PC.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.345-352
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• 2001

In this paper, a VoIP (Voice on Internet Protocol) terminal system, which can process voice in real time based on Linux, is designed and implemented. The hardware of it is designed using a i486 processor and a DSP codec chip which encodes and decodes voice data in real time. As an operating system, RTLinux, which is a real-time operating system based on Linux, is ported to manage real-time voice processing. The voice processing module of the system uses G.723.1 voice codec of ITU-T standard. It transfers voice data within 30ms to assure good voice quality. In order to satisfy the real time requirements and QoS (Quality-of-Service) for the voice data, the real-time voice processing device driver is designed and implemented. To verify the system, the chatting application program is developed and tested for QoS of the system.