• Proceedings of the KOSOMBE Conference
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• v.1996 no.05
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• pp.320-324
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• 1996

Digital fetal monitoring system based on the personal computer combined with the digital signal processing board was implemented. The DSP board acquires and digitally processes ultrasound fetal Doppler signal for digital rectification, FIR filtering, autocorrelation function calculation, its peak detection and MEDIAN filtering. The personal computer interfaced with the DSP board is in charge of graphic display, hardcopy, data transmission and on-line analysis of fetal heart rate change including and variability. I used a recursive technique for autocorrelation function computation method and MEDIAN filter which can greatly reduce the amount of calculation and accuracy. I also implemented analysis algorithm of fetal heart rate change based on normal fetal sample data in order to exact diagnosis.

• The Journal of the Acoustical Society of Korea
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• v.40 no.1
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• pp.46-54
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• 2021

In this paper, active noise control was performed to reduce radiated noise in the low frequency band of dishwashers. First, through an analysis of the noise environment of the dishwasher, it was confirmed that the pump noise contributed the most to the radiated noise in the low frequency band, From the result of the noise environment analysis, the reference signal was selected to be the vibration signal of the pump body. The reference signal was obtained by using the accelerometer on the pump body, which can prevent acoustic feedback. The error signal sensor was selected as a microphone located at 1 m in front of the dishwasher and 0.5 m in height. And to design the controller, the error signal and the reference signal were measured at the operational rpms of the dishwasher at 2,500 rpm, 2,600 rpm and 2,800 rpm, and the secondary path transfer function was measured. The designed controller was mounted on Digital Signal Processor (DSP) equipment, and the control performance was verified experimentally. As a result of the measurement at the 3 operational rpms, the 7th multiple component of pump operating frequency decreased by 1.93 dB, 4.43 dB, 5.15 dB per rpm, and the 12th multiple component decreased by 6.67 dB, 2.34 dB, 4.28 dB per rpm. And overall Sound Pressure Level (SPL) decreased by 0.84 dB, 2.58 dB, 1.48 dB by rpm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.53-61
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• 2002

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1956-1959
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• 2003

본 논문에서는 HDTV(High Definition TV) 방송수신을 위한 DSP(Digital Signal Processor)기반의 HD급 비디오/오디오 디코더 시스템을 개발하고 그 성능을 확인하였다. DSP 플랫폼은 TI(Texas Instrument)사의 TMS320C6415를 대상으로 하였으며 TI의 DSP RTOS인 DSP/ BIOS를 이용하여 방송스트림인 TS(Transport Stream)을 분리하기 위한 TS Demuxer, MPEG-2 비디오 디코더 및 AC-3 오디오디코더 알고리즘을 통합하였으며, 각각의 알고리즘은 대상 DSP플랫폼인 TMS320C64x에 맞게 고정소수점 구조화 및 최적화를 실시하였다. 테스트를 위한 시스템은 스트리밍을 위한 호스트 PC와 PCI(Peripheral Component Interconnect)버스를 통해 연결된 DSP보드로 구성하였으며 실제 HDTV당송용 스트림과 SD(Standard Definition)급 스트림을 이용하여 성능을 확인하였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.1
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• pp.25-30
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• 2023

We propose a method to update DSP (Digital Signal Processor) firmware using USB (Universal Serial Bus) flash drives. The DSP automatically detects USB drives based on an interrupt when the USB drive is inserted into the USB port. The new firmware binary file is found in the mounted USB drive, and the destination address of DSP flash memory is identified for the firmware update writing by investigating the firmware file header. After the new firmware is written to the DSP flash memory, the DSP is reset and rebooted with the newly updated firmware. By employing TI's TMS320F28379D control card with USB ports, we conduct experiments and verify the normal operation of the implemented method.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1211-1214
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• 1998

Real-time implementation of Conjugate-Structure Algebraic CELP(CS-ACELP) is presented. ITU-T Study Group(SG) 15 has standardized the CS-ACELP speech coding algorithm as G.729. A real-time implementation of the CS-ACELP is achieved using 16 bit fixed point DSP16210 Digital Signal Processor (DSP) of Lucent Technologies. The speech coder has been implemented in the bit-exact manner using the fixed point CS-ACELP C source which is the part of the G.729 standard. To provide a multi-channel vocoder solution to digital communication system, we try to minimize the complexity(e.g., MIPS, ROM, RAM) of CS-ACELP. Our speech coder shows 15.5 MIPS in performance which enables 4 channel CS-ACELP to be processed with one DSP16210.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1406-1409
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• 2004

The Resolver usually used in industry is the absolute angle analog sensor that must be in order to driving BLDC (brushless DC) motor, and it needs RDC(Resolver-to-Digital converter) for changing the output signal to digital to be applied to the SVPWM(Space Vector Pulse Width Modulation) algorithm. Commonly used S/W RDC needs trigonometric function. What it takes a lot of calculation time of processor is gotten at weak point. In this paper, S/W RDC is realized except trigonometric functions as a result of feedback resolver outputs after filtering using FIR filter. thus, processing time is reduced. So, One-chip DSP Controller operating the Vector Control, RDC, and SVPWM can be designed.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.988-990
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• 2000

This paper presents the software control of a brush-less DC motor. Not only speed and current controls but also a real-time identification of the motor parameters can be implemented by software using the digital signal processor (DSP) TMS320F240. The DSP Controller TMS320F240 from Texas Instruments is suitable for a wide range of motor drives. TMS320F240 provides a single chip solution by integrating on-chip not only a high computational power but also all the peripherals necessary for electric motor control. The main benefits are increased system reliability and cost reduction of the overall system. The present paper describes how a speed controlled brushless DC drive can be implemented using TMS320F240.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.282-285
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• 2000

Three representations are known to implement the discrete wavelet transform (DWT) ; i.e., direct, lifting and matrix forms. In these representations, direct and lifting forms are well known so far. This paper derives the matrix form of the DWT from the direct form. Then, we implement these three representations on a programmable digital signal processor (in the following, DSP processor) and compare them in terms of the number of calculations and instruction cycles. As a result, we confirm that the lifting form has the lowest number of calculations and cycles, and the matrix form has an effective decrease in the number of cycles than other representations on the DSP processor.