• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.247-249
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• 1988

The most space-consuming element of digital image processing system is the video memory. Though this problem is solved by DRAMs, timing constraints posed by video data rates. The cycle time of DRAMs can be diminished by serial transferring and reading or writing pixel datas at the same time. This paper resents the design of 1024${\times}$512 video memory using this technique.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.138-144
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• 1995

It is commonly believed that high permittivity materials will be necessary for future high density Gbit DRAMs. In a first part, we explain the choice of SrTiO3 by ECR MOCVD for Gbit-scale DRAMs. In a second part, after describing the ECR MOCVD system and presenting the requirements SrTiO3 thin films should meet for use in Gbit-scale DRAMs, the physical and electrical properties of srTiO3 thi film prepared by ECR MOCVD are then studied. A stacked capacitor technology, suitable for use in 1 Gbit DRAM, and comprising high permittivity SrTiO3 thin films prepared by ECR MOCVD at $450^{\circ}C$ on electron beam and RIE patterned RuO2/TiN storage nodes is finally described.

• Electronics and Telecommunications Trends
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• v.8 no.2
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• pp.14-31
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• 1993

DRAM은 거의 20여년 동안 반도체산업의 기술 원동력이었으며, 앞으로도 10여년 이상은 계속 그러하리라고 본다. 우리나라의 반도체 산업은 주로 DRAM 부문에 집중되어 있다. '92년에 단일 품목으로 세계 반도체 시장의 약 25%를 점하였으며, 특히 미국에 대한 수출은 약 8억 5천만 달러에 이르는 등 우리나라 수출 및 전자산업에서 차지하는 비중은 대단히 높다. 세계적인 주요 반도체 대기업들은 상호동맹관계를 형성하거나 덤핑제소 등으로 우리의 능력을 약화시키려고 한다. 우리는 이러한 국제적 동향에 능동적이고 적극적으로 대처하여야 한다. 본고는 과기처 특정연구사업으로 미국측에 위탁과제로 수행하고 있는 내용 중에서 현재 세계 반도체산업의 기술추세 및 당면하고 있는 중요한 몇가지 문제점들을 살펴보고 우리가 취해야 할 몇가지 방향을 제시하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.3
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• pp.3-7
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• 2010

As the distance between signal lines in memories of high density ICs like SoCs decreases rapidly, failure occurs more frequently and effective memory test techniques are needed. In this paper, a new SRAM structure is proposed to decrease test complexity and test time for embedded DRAMs. In the presented technique, because memory test can be handled as a single port testing and read-write operation is possible at dual port without high complexity, test time can be much reduced.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.145-150
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• 1995

PZT thin films were fabricated on Pt/Ti/SiO2/Si substrates at $500^{\circ}C$ by ECR-PECVD for the application to the charge storage capacitor of ULSI DRAMs. Perovskite single phase PZT films were obtained by controling the film compositional ratio Pb/(Zr+Ti) close to 1. The anion concentrations in the PZT films were successfully controlled by adjusting the flow rates of each MO sources. Capacitance of a typical 94 nm thick PZT film prepared at $500^{\circ}C$ in this work was about 5.3 uF/$\textrm{cm}^2$, which corresponds to the equivalent SiO2 thickness of 0.65nm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.442-446
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• 2003

This paper proposes a new two-stage two-phase VPP charge pump configured in such a manner that body effect and the threshold voltage loss are eliminated. The newly proposed circuit is fabricated using 0.18um triple-well CMOS process and the measurement result shows that the VPP level tracks 3VDD when VDD is above the threshold voltage.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.82-87
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• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.251-265
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• 2001

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.8
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• pp.1290-1298
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• 1989

A new dynamic RAM cell called Trench Epitaxial Transistor Cell (TETC) has been developed for 4M to 16M DRAMS. Also the fabrication process for device isolation which can decrease the narrow effect using SEG process has been developed. We verified the characteristic of the new cell structure with the PICSES simulator on VAX8450.