• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.98-104
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• 2013

This paper presents a WBAN UWB receiver circuit for RTLS(real time location system) and wireless data communication. The UWB receiver is designed to OOK modulation for energy detection. The UWB receiver is designed for sub-sampling techniques using 4bit ADC and DLL.The proposed UWB receiver is designed in $0.18{\mu}m$ CMOS and consumes 61mA with a 1.8V supply voltage. The UWB receiver achieves a sensitivity of -85.7 dBm, a RF front-end gain of 42.1 dB, a noise figure of 3.88 dB and maximum sensing range of 4 meter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12B
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• pp.1695-1702
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• 2001

This paper describes a design of CMOS infrared (IR) wireless data link IC which can be used in IrDA(Infrared Data Association) application from 4 Mb/s to 100 Mb/s The implemented chip consists of variable gain transimpedance amplifier which has a gain range from 60 dB to 100 dB, AGC (automatic gain control) circuits, AOC(automatic offset control) loop, 4 PPM (pulse position modulation) modulator/demodulator and DLL(delay locked loops). This infrared optical link If was implemented using commercial 0.25 um 1-poly 5-metal CMOS process. The chip consumes 25 mW at 100 Mb/s with 2.5 V supply voltage excluding buffer amplifier. The die area of prototype IC is 1.5 mm $\times$ 1 mm.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.142-144
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• 2004

본 논문은 Windows CE의 파일 시스템을 개발하기 위해 필요한 Windows CE .NET 4.0이 제공하는 Platform Builder 통합 개발 환경 툴을 이용하여 파일 시스템 필터를 사용하여 파일시스템을 설계한다. 그리고, Windows CE 에서 사용하는 파일 시스템 필터 encfilt.dll를 이용하여 Windows CE 파일 시스템을 개발할 수 있는 환경을 설정한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.67-73
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• 2015

This paper presents a fully integrated 3 - 5 GHz IR-UWB(impulse radio ultra-wide band) RFIC for Location based system. The receiver architecture adopts the energy detection method and for high speed sampling, the equivalent time sampling technique using the integrated DLL(delay locked loop) and 4 bit ADC. The digitally synthesized UWB impulse generator with low power consumption is also designed. The designed IR-UWB RFIC is implemented on $0.18{\mu}m$ CMOS technology. The receiver's sensitivity is -85.7 dBm and the current consumption of receiver and transmitter is 32 mA and 25.5 mA respectively at 1.8 V supply.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.325-332
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• 2004

In this paper, we propose a new DSSS-QPSK baseband modem receiver structure. A general receiver consists of matched filter, do-spreader, and DLL(Delay Locked Loop). In this paper, the matched filter plays a role of the do-spreader using the structure similarities between the matched filter and the de-spreader. As a result of the new receiver architecture, we can reduce the computational expenses and get the simpler receiver structure. This result can be used as an important part in designing the high speed modem. And, through the computer simulation and the experiment with the proposed architecture, we show that the proposed receiver structure yields fast operation speed and simple overall architecture.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.496-499
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• 1997

This paper describes the operating software of a motion system developed for a driving simulator, consisting of a six degree of freedom Stewart platform driven hydraulically. The drive logic, consisting of an washout algorithm, inverse kinematic analysis, and a control algorithm, has been developed and applied for creating high fidelity motion cues. The basic environment of the operating software is based on LabVIEW 4.0 and DLL modules compiled by Fortran.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.4
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• pp.593-603
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• 2020

The advent of malicious code has increased exponentially due to the spread of malicious code generation tools in accordance with the development of the network, but there is a limit to the response through existing malicious code detection methods. According to this situation, a machine learning-based malicious code detection method is evolving, and in this paper, the feature of data is extracted from the PE header for machine-learning-based malicious code detection, and then it is used to automate the malware through autoencoder. Research on how to extract the indicated features and feature importance. In this paper, 549 features composed of information such as DLL/API that can be identified from PE files that are commonly used in malware analysis are extracted, and autoencoder is used through the extracted features to improve the performance of malware detection in machine learning. It was proved to be successful in providing excellent accuracy and reducing the processing time by 2 times by effectively extracting the features of the data by compressively storing the data. The test results have been shown to be useful for classifying malware groups, and in the future, a classifier such as SVM will be introduced to continue research for more accurate malware detection.

• The Journal of the Korea Contents Association
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• v.13 no.3
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• pp.22-31
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• 2013

For the case of test equipments requiring data accuracy, real-time is highly required in acceptance test for performance evaluation of developed weapons. For convenience' sake, test equipments are usually developed using Windows. However Windows does not support real-time in itself. Thus, in this paper, so as to reduce development time and expenses, we design and implement an integrated middleware for real-time device drivers using RTiK-MP. Using DLL, we also support user API's for the sake of development convenience without details of the complex RTiK-MP structure. We evaluate the performance of the proposed integrated middleware using the RDTSC command which returns the number of CPU clock ticks. The evaluation results show that it operates correctly within error ranges in the periods of 1ms and 4ms for the cases of TCP/IP and RS-232, respectively.