• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.648-651
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• 2001

This paper describes the 8-error-correction (204, 188) Reed-Solomon Decode. over GF(2$^{8}$ ) for a satellite communication. It is synthsized using a CMOS library. Decoding algorithm of Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to slove error-values. The decoder is designed using Modified Euclid algorithm in this paper. First of all, The functionalities of the circuit are verified through C++ programs, and then it is designed in Verilog HDL. It is verified through the logic simulations of each blocks. Finally, The Reed-Solomon Decoder is synthesized with Synopsys Tool.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.75-82
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• 2006

In this paper, a space-frequency coded orthogonal frequency division multiplexing (SFC-OFDM) scheme with dual Viterbi decoder is proposed and analyzed. Here, two independent half-rate OFDM symbols are generated after convolutional coding of the binary source code. A dual Viterbi decoder is exploited to decode the demodulated sequences independently in the receiver, and their path metrics are compared. Accordingly, the recovered binary data in the proposed scheme are composed of the combination of the sequences having larger path metrics while those in a conventional system are simply the output of single Viterbi decoder. As a result, the proposed SFC-OFDM scheme has a better performance than the conventional one for all signal-to-noise power ratio.

• ETRI Journal
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• v.28 no.3
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• pp.301-310
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• 2006

In mobile communications, a class of variable-complexity algorithms for convolutional decoding known as sequential decoding algorithms is of interest since they have a computational time that could vary with changing channel conditions. The Fano algorithm is one well-known version of a sequential decoding algorithm. Since the decoding time of a Fano decoder follows the Pareto distribution, which is a heavy-tailed distribution parameterized by the channel signal-to-noise ratio (SNR), buffers are required to absorb the variable decoding delays of Fano decoders. Furthermore, since the decoding time drawn by a certain Pareto distribution can become unbounded, a maximum limit is often employed by a practical decoder to limit the worst-case decoding time. In this paper, we investigate the relations between buffer occupancy, decoding time, and channel conditions in a system where the Fano decoder is not allowed to run with unbounded decoding time. A timeout limit is thus imposed so that the decoding will be terminated if the decoding time reaches the limit. We use discrete-time semi-Markov models to describe such a Fano decoding system with timeout limits. Our queuing analysis provides expressions characterizing the average buffer occupancy as a function of channel conditions and timeout limits. Both numerical and simulation results are provided to validate the analytical results.

• Journal of IKEEE
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• v.20 no.3
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• pp.326-329
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• 2016

HEVC CABAC encoder performs binary arithmetic encoding after syntax elements are converted into binary values. Therefore, in HEVC CABAC decoder, binarized syntax elements from binary arithmetic decoder should be de-binarized into original syntax elements in the de-binarizer. In this paper, a HEVC CABAC de-binarizer architecture was proposed and implemented. It consists of a controller that analyzes and merges binarized syntax elements and an engine that converts merged binarized syntax elements into original syntax elements. The designed de-binarizer was described in Verilog HDL and it was synthesized and verified in 0.18um process technology. Its gate count and maximum operating frequency are 3,114 gates and 220 MHz, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.287-294
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• 2010

MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2525-2532
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• 2009

In this paper, a fast sphere decoder is proposed for the joint detection of phase-shift keying (PSK) signals in uncoded Vertical Bell Laboratories Layered Space Time (V-BLAST) systems. The proposed decoder, PSD, consists of preprocessing stage and search stage. The search stage of PSD relies on the depth-first branch-and-bound (BB) algorithm with "best-first" orders stored in lookup tables. Simulation results show that the PSD is able to provide the system with the maximum likelihood (ML) performance at low complexity.

• Journal of Broadcast Engineering
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• v.12 no.6
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• pp.641-648
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• 2007

The decoding structure of up-to-date ATSC DTV receivers is well optimized, and it seems that 14.6 dB is the unbreakable minimum SNR in the AWGN channel. But the SNR satisfying the Shannon capacity of DTV receivers is 11.76 dB, So, the SNR gab between the 14.6 dB and the 11.76 dB is about 2.8 dB. In order to approach the Shannon capacity we propose a recursive trellis decoder which uses reliable feedback data obtained by an RS decoder. The performance enhancement of about 0.8 dB can be achieved in case of the AWGN channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.432-438
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• 2011

This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.798-801
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• 2010

This paper describes an efficient architecture for LDPC(Low-Density Parity Check) decoder, which supports three block lengths (648, 1,296, 1,944) of IEEE 802.11n standard. To minimize hardware complexity, the min-sum algorithm and block-serial layered structure are adopted in DFU(Decoding Function Unit) which is a main functional block in LDPC decoder. The optimized H-ROM structure for multi block lengths reduces the ROM size by 42% as compared to the conventional method. Also, pipelined memory read/write scheme for inter-layer DFU operations is proposed for an optimized operation of LDPC decoder.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.47 no.2
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• pp.161-168
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• 2019

This paper proposes a variable data transfer asymmetric TDD(Time Division Duplex) system for small UAV(Unmanned Aerial Vehicle) data link system. In the proposed method, a turbo decoder with a double buffer controller is proposed to apply turbo decoder with long decoding time to asymmetric TDD system. The proposed method achieves variable data transfer rate and maximum data transfer rate. The advantage of the proposed method is demonstrated by its data transfer rate. The measured data transfer rate is more than 1.8 times than that of symmetric TDD system. In addition, PER(Packet Error Rate) performance is the same and data transfer rate is variable.