• The KIPS Transactions:PartB
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• v.12B no.6 s.102
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• pp.637-646
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• 2005

Most of the multimedia contents for DBM services art provided as MPEG-2 bit streams. However, they have to be transcoded to H.264 bit streams for practical services because the standard video codec for DMB is H.264. The existing transcoder architecture is Cascaded Pixel-Domain Transcoding Architecture, which consists of the MPEG-2 dacoding phase and the H.264 encoding phase. This architecture can be easily implemented using MPEG-2 decoder and H.264 encoder without source modifying. However. It has disadvantages in transcoding time and DCT-mismatch problem. In this paper, we propose two kinds of transcoder architecture, DCT-OPEN and DCT-CLOSED, to complement the CPDT architecture. Although DCT-OPEN has lower PSNR than CPDT due to drift problem, it is efficient for real-time transcoding. On the contrary, the DCT-CLOSED architecture has the advantage of PSNR over CPDT at the cost of transcoding time.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• KIISE Transactions on Computing Practices
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• v.23 no.3
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• pp.183-187
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• 2017

Smart phone users prefer fast reading and texting. Hence, users frequently use abbreviated sequences of words and phrases. Nowadays, abbreviations are widely used from chat terms to technical terms. Therefore, gathering abbreviations would be helpful to many services, including information retrieval, recommendation system, and so on. However, manually gathering abbreviations needs to much effort and cost. This is because new abbreviations are continuously generated whenever a new material such as a TV program or a phenomenon is made. Thus it is required to generate of abbreviations automatically. To generate Korean abbreviations, the existing methods use the rule-based approach. The rule-based approach has limitations, in that it is unable to generate irregular abbreviations. Another problem is to decide the correct abbreviation among candidate abbreviations generated rules. To address the limitations, we propose a method of generating Korean abbreviations automatically using sequence-to-sequence learning in this paper. The sequence-to-sequence learning can generate irregular abbreviation and does not lead to the problem of deciding correct abbreviation among candidate abbreviations. Accordingly, it is suitable for generating Korean abbreviations. To evaluate the proposed method, we use dataset of two type. As experimental results, we prove that our method is effective for irregular abbreviations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.523-529
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• 2017

In this paper, we propose an efficient sphere decoding scheme that reduces computational complexity by combining receive and transmit ordering techniques in generalized spatial modulation systems, where the indexes of activated transmit antennas as well as the transmit symbols are exploited to transfer information to the receiver. In this scheme, the receive signals are optimally ordered so that the calculation for a candidate solution outside the sphere is terminated early to lower the computational complexity. In addition, the transmit ordering technique is applied to first search for candidate symbols and activated antennas having higher probabilities to further reduce the computational complexity. Simulation results show that the proposed doubly ordered sphere decoding scheme provides the same bit error rate performance with the conventional sphere decoding method and the sphere decoder employing only the receive ordering technique while it requires lower computational complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8C
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• pp.575-582
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• 2008

In this paper we described the process and the results of real-time implementation of G.729.1 wideband speech codec which is standardized in SG15 of ITU-T. To apply the codec on ARM926EJ-S(R) processor core. we transformed some parts of the codec C program including basic operations and arithmetic functions into assembly language to operate the codec in real-time. G.729.1 is the standard wideband speech codec of ITU-T having variable bit rates of $8{\sim}32kbps$ and inputs quantized 16 bits PCM signal per sample at the rate of 8kHz or 16kHz sampling. This codec is interoperable with the G.729 and G.729A and the bandwidth extended wideband($50{\sim}7,000Hz$) version of existing narrowband($300{\sim}3,400Hz$) codec to enhance voice quality. The implemented G.729.1 wideband speech codec has the complexity of 31.2 MCPS for encoder and 22.8 MCPS for decoder and the execution time of the codec takes 11.5ms total on the target with 6.75ms and 4.76ms respectively. Also this codec was tested bit by bit exactly against all set of test vectors provided by ITU-T and passed all the test vectors. Besides the codec operated well on the Internet phone in real-time.

• Journal of Broadcast Engineering
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• v.11 no.4 s.33
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• pp.386-395
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• 2006

Multi-view video coding technology demands the very high efficient coding technologies, because it has to encode a number of video sequences which are achieved from a number of video cameras. For this purpose, multi-view video coding introduces the inter-view prediction scheme between different views, but it shows a limitation of coding performance enhancement by adopting only new prediction method. Accordingly, we are going to achieve the more coding performance by enhancing dequantizer perfermance. Multi-view video coding is implemented basically based on H.264/AVC and uses the same quantization/de-quantization method as H.264/AVC does. The conventional quantizer and dequantizer is designed with the assumption that input residual signal follows the Laplacian PDF. However, it doesn't follow the fixed PDF type always. This mismatch between assumption and real data causes degradation of coding performance. To solve this problem, we propose the efficient de-quantization method based on quantized coefficients distribution at decoder without extra information. The extensive simulation results show that the proposed algorithm produces maximum $1.5\;dB{\sim}0.6\;dB$ at high bitrate compared with that of conventional method.

• The Journal of the Acoustical Society of Korea
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• v.22 no.7
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• pp.592-602
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• 2003

This paper aims to describe the basic structure of novel object-based 3D audio broadcasting system To overcome current uni-directional audio broadcasting services, the object-based 3D audio broadcasting system is designed for providing the ability to interact with important audio objects as well as realistic 3D effects based on the MPEG-4 standard. The system is composed of 6 sub-modules. The audio input module collects the background sound object, which is recored by 3D microphone, and audio objects, which are recorded by monaural microphone or extracted through source separation method. The sound scene authoring module edits the 3D information of audio objects such as acoustical characteristics, location, directivity and etc. It also defines the final sound scene with a 3D background sound, which is intended to be delievered to a receiving terminal by producer. The encoder module encodes scene descriptors and audio objects for effective transmission. The decoder module extracts scene descriptors and audio objects from decoding received bistreams. The sound scene composition module reconstructs the 3D sound scene with scene descriptors and audio objects. The 3D sound renderer module maximizes the 3D sound effects through adapting the final sound to the listner's acoustical environments. It also receives the user's controls on audio objects and sends them to the scene composition module for changing the sound scene.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.9 s.351
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• pp.149-157
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• 2006

Turbo code, a kind of error correction coding technique, has been used in the field of digital mobile communication system. As the number of iterations increases, it can achieves remarkable BER performance over AWGN channel environment. However, if the number of iterations is increased in the several channel environments, any further iteration results in very little improvement, and requires much delay and computation in proportion to the number of iterations. To solve this problems, it is necessary to device an efficient criterion to stop the iteration process and prevent unnecessary delay and computation. In this paper, it proposes an efficient and simple criterion for stopping the iteration process in turbo decoding. By using variance values of LLR in turbo decoder, the proposed algerian can largely reduce the average number of iterations without BER performance degradation in all SNR regions. As a result of simulation, the average number of iterations in the upper SNR region is reduced by about $34.66%{\sim}41.33%$ compared to method using variance values of extrinsic information. the average number of iterations in the lower SNR region is reduced by about $13.93%{\sim}14.45%$ compared to CE algorithm and about $13.23%{\sim}14.26%$ compared to SDR algorithm.