• IEIE Transactions on Smart Processing and Computing
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• v.3 no.5
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• pp.251-258
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• 2014

This paper proposes an efficient token flow design methodology for a decoder in the MPEG Reconfigurable Media Coding (RMC) framework. The MPEG RMC framework facilitates a decoder to be configured with a set of modules called functional units (FUs) that are connected by tokens. Such a modular design philosophy of the MPEG RMC framework enables the reusability and reconfigurability of FUs. One drawback of the MPEG RMC framework is that the decoder performance can be affected by increasing the token transmissions between FUs. The proposed method improves the design of the FU network in the RMC framework toward real-time decoder implementation. In the proposed method, the merging of FU, the separation of token flow, and the merging of token transactions are applied to minimize the token traffic between FUs. The experimental results of the MPEG-4 SP decoder show that the proposed method reduces the total decoding time by up to 77 percent compared to the design of the RMC simulation model.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.423-426
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• 2005

In this paper, we propose a receiver that combines a channel detector with a channel decoder to retrieve information from ISI and AWGN in an iteratively manner. The receiver, evolving from a system of a PRML detector and a RS decoder, consists of a SOVA detector followed by a LDPC decoder and has them exchange information iteratively. Rather than handling extrinsic reliabilities explicitly as in Turbo equalization, we take hard-decision values from the LDPC decoder and mix them with the channel output in a certain ratio as input for SOVA. The scheme, simply modified to the one-way structure of a SOVA and a LDPC decoder, shows improved performance with iteration numbers as well as the combining ratio of the channel output and the feedback output. We additionally analyze the receiver with a simple theoretical model and present some valuable properties.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.61-66
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• 2001

In this paper, we design high speed Viterbi decoding algorithm which is aimed for Wireless LAN. Wireless LAN transmits data at rate 6∼54 Mbps. This high speed is not easy to implement Viterbi decoder with single ACS. So parallel ACS butterfly structure is to be used and several time-dependent problem is to be solved. We simulate Viterbi algorithm using new branch metric calculating method to save time, and consider trace back algorithm which is adaptable to high speed Viterbi decoder. With simulated, we determine the structure of Viterbi decoder. This architecture is available to high speed and low power Viterbi decoder.

• Journal of Broadcast Engineering
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• v.9 no.2
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• pp.119-130
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• 2004

We have developed a prototype super-high-definition (SHD) digital cinema distribution system that can store, transmit, and display eight-million-pixel motion pictures that have the image quality of a 35-mm film movie. The system contains a movie server, a real-time decoder, and an SHB projector. Using a Gigabit Ethernet link and TCP/IP, the server transmits JPEG2000 compressed motion picture data streams to the decoder at transmission speeds as high as 300 Mbps. The received data streams are decompressed by the decoder, and then projected onto a screen via the projector. By using an enlarged TCP window, multiple TCP streams, and a shaping function to control the data transmission quantity, we achieved real-time streaming of SHD movie data at about 300 Mbps between Chicago and Los Angeles, a distance of more than 3000 km. We also improved the decoder performance to show movies with Image qualities of 450 Mbps or higher. Since UDP is more suitable than TCP for fast long-distance streaming, we have developed an SHD digital cinema UDP relay system, in which UDP is used for transmission over a fast long-distance network. By using four pairs of server-side-proxy and decoder-side-proxy, 450-Mbps movie data streams could be transmitted.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.550-556
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• 2016

Polar codes are one of the most favorable capacity-achieving codes due to their simple structure and low decoding complexity. However, because of the disappointing decoding performance realized using conventional successive cancellation (SC) decoders, polar codes cannot be used directly in practical applications. In contrast to conventional SC decoders, list SC (SCL) decoders with large list sizes (e.g. 32) achieve performances very close to those of maximum-likelihood (ML) decoders. In SCL decoders with large list sizes, however, hardware increase is a severe problem because an SCL decoder with list size L consists of L copies of an SC decoder. In this paper, we present a low-area SCL decoder architecture that applies the proposed merged processing element-sharing (MPES) algorithm. A merged processing element (MPE) is the basic processing unit in SC decoders, and the required number of MPEs is L(N-1) in conventional SCL decoders. Using the proposed algorithm reduces the number of MPEs by about 70% compared with conventional SCL decoders when the list size is larger than 32.

• Aerospace Engineering and Technology
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• v.8 no.1
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• pp.179-186
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• 2009

This paper describes the design and implementation for spread spectrum FTS encoder and decoder. The FTS command format is defined by 64 bit encrypted packet that contains all required information relayed between the ground and the vehicle. Encryption is accomplished using the Tripple-DES encryption algorithm in block encryption form. The proposed FTS encoder and decoder is using the Convolution Encoding and Viterbi Decoding for forward error correction. The Spread Spectrum Modulation is done using a PN code, which is 256 bit gold code. The simulation result shows that the designed FTS decoder is compatible with the designed FTS encoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.775-783
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• 2006

In this paper, the new technique combining beamforming with space-time coding is proposed for an orthogonal frequency division multiplexing(OFDM) system with multi-input multi-output(MIMO). When MIMO-OFDM system is employing Nt(the number of transmitterantenna) beamfomers and one S-T decoder at Nr receiver antennas, Nt signals removed CCI are outputted at the beamformer and then diversity gain can be got through space-time decoding. As the proposed technique can reduce cochannel interference and get diversity gain in the multi-user environment, the performance of MIMO-OFDM system is very improved. BER performance improvement and convergence behavior of the proposed approach are investigated through computer simulation by applying it to MIMO-OFDM system in the multi-user environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12A
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• pp.1333-1339
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• 2004

In IS-95 and IMT-2000 systems using variable code rates and constraint lengths, this paper limits code rate 1/2 and constraint length 3 and states the effective reduction of PM(Path Metric) and BM(Branch Metric) memories and arithmetic comparative calculations with appling PVSL(Prototype Vector Selecting Logic) and LVQ(Learning Vector Quantization) in neural network to simplify systems and to decode forwardly. Regardless of extension of constraint length, this paper presents the new Vierbi decoder and the appied algorithm because new structure and algorithm can apply to the existing Viterbi decoder using only uncomplicated application and verifies the rationality of the proposed Viterbi decoder through VHDL simulation and compares the performance between the proposed Viterbi decoder and the existing.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.