• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.121-145
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• 2001

Chip Size Packages (CSP) are now widely used in high speed DRAM. The major driving farce of CSP development is its superior electrical performance than that of conventional package. However, the power dissipation of high speed DRAM like DDR or RAMBUS DRAM chip reaches up to near 2W. This fact makes the thermal management methods in DRAM package be more carefully considered. In this study, the thermal performances of 3 type CSPs named $\mu-BGA$^{TM}$$ $UltraCSP^{TM}$ and OmegaCSP$^{TM}$ were measured under the JEDEC specifications and their thermal characteristics were of a simulation model utilizing CFD and FEM code. The results show that there is a good agreement between the simulation and measurement within Max. 10% of $\circledM_{ja}$. And they show the wafer level CSPs have a superior thermal performance than that of $\mu-BGA.$ Especially the analysis results show that the thermal performance of wafer level CSPs are excellent fur modulo level in real operational mode without any heat sink.

• Transactions of the Korean hydrogen and new energy society
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• v.22 no.6
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• pp.868-877
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• 2011

This paper presents a parallel computing methodology for polymer electrolyte fuel cells (PEFCs) and detailed simulation contours of a real-scale fuel cell. In this work, a three-dimensional two-phase PEFC model is applied to a large-scale 200 $cm^2$ fuel cell geometry that requires roughly 13.5 million grid points based on grid-independence study. For parallel computing, the large-scale computational domain is decomposed into 12 sub-domains and parallel simulations are carried out using 12 processors of 2.53 GHz Intel core i7 and 48GB RECC DDR3-1333. The work represents the first attempt to parallelize a two-phase PEFC code and illustrate two-phase contours in a representative industrial cell.

• Genomics & Informatics
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• v.12 no.4
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• pp.247-253
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• 2014

Osteosarcoma is the most common primary bone tumor, generally affecting young people. While the etiology of osteosarcoma has been largely unknown, recent studies have suggested that cyclooxygenase-2 (COX-2) plays a critical role in the proliferation, migration, and invasion of osteosarcoma cells. To understand the mechanism of action of COX-2 in the pathogenesis of osteosarcoma, we compared gene expression patterns between three stable COX-2-overexpressing cell lines and three control cell lines derived from U2OS human osteosarcoma cells. The data showed that 56 genes were upregulated, whereas 20 genes were downregulated, in COX-2-overexpressed cell lines, with an average fold-change > 1.5. Among the upregulated genes, COL1A1, COL5A2, FBN1, HOXD10, RUNX2, and TRAPPC2 are involved in bone and skeletal system development, while DDR2, RAC2, RUNX2, and TSPAN31 are involved in the positive regulation of cell proliferation. Among the downregulated genes, HIST1H1D, HIST1H2AI, HIST1H3H, and HIST1H4C are involved in nucleosome assembly and DNA packaging. These results may provide useful information to elucidate the molecular mechanism of the COX-2-mediated malignant phenotype in osteosarcoma.

• ETRI Journal
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• v.44 no.3
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• pp.450-461
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• 2022

The Gen-Z protocol is a memory semantic protocol between the memory and CPU used in computer architectures with large memory pools. This study presents the implementation of the Gen-Z hardware system configured using Gen-Z specification 1.0 and reports its performance. A hardware prototype of a DDR4 Gen-Z memory pool with an optimized character, a block device driver, and a file system for the Gen-Z hardware was designed. The Gen-Z IP was targeted to the FPGA, and a 512 GB Gen-Z memory pool was configured on an ×86 server. In the experiments, the latency and throughput of the Gen-Z memory were measured and compared with those of the local memory, SATA SSD, and NVMe using character or block device interfaces. The Gen-Z hardware exhibited superior throughput and latency performance compared with SATA SSD and NVMe at block sizes under 4 kB. The MySQL and File IO benchmark of Gen-Z showed good write performance in all block sizes and threads. Besides, it showed low latency in RocksDB's fillseq dbbench using the ext4 direct access filesystem.

• Journal of IKEEE
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• v.19 no.3
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• pp.288-294
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• 2015

CRC function has been built into the high-speed semiconductor memory device in order to increase the reliability of data for high-speed operation. Also, DBI function is adopted to improve of data transmission speed. Conventional CRC(ATM-8 HEC code) method has a significant amounts of area-overhead(~XOR 700 gates), and processing time(6 stage XOR) is large. Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC calculations. In this paper, we propose a CRC method for low cost and high speed memory, which was improved 92% for area-overhead. For low-cost implementation of the CRC scheme by the DBI function it was supplemented by data bit error detection rate. And analyzing the error detection rate were compared with conventional CRC method.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.67-75
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• 2007

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

• Journal of Advanced Navigation Technology
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• v.13 no.6
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• pp.957-963
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• 2009

It is necessary for the resource management system to manage for the resource in distributed networking environment. Because of increasing the complexity of vast computer system and business environment, needs of RMS is increasing. Based on the common information model to use of objected oriented technology, through analysis of the reference model for the resource management system of the SNIA, we intend to implement the application program to manage the NGS system that consist of SSD and DRAM. To visualize, it is use the GUI Interface. It is possible for application program(Client) to detect and manage the system that consist of the NGS system. Also, status information that is divided into three cataloges(Minor/Major/Critical) can be displayed and it provide support of configuration functionality to manage devices.

• Journal of Ginseng Research
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• v.44 no.1
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• pp.79-85
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• 2020

Background: Helicobacter pylori increases reactive oxygen species (ROS) and induces oxidative DNA damage and apoptosis in gastric epithelial cells. DNA damage activates DNA damage response (DDR) which includes ataxia-telangiectasia-mutated (ATM) activation. ATM increases alternative reading frame (ARF) but decreases mouse double minute 2 (Mdm2). Because p53 interacts with Mdm2, H. pylori-induced loss of Mdm2 stabilizes p53 and induces apoptosis. Previous study showed that Korean Red Ginseng extract (KRG) reduces ROS and prevents cell death in H. pylori-infected gastric epithelial cells. Methods: We determined whether KRG inhibits apoptosis by suppressing DDRs and apoptotic indices in H. pylori-infected gastric epithelial AGS cells. The infected cells were treated with or without KRG or an ATM kinase inhibitor KU-55933. ROS levels, apoptotic indices (cell death, DNA fragmentation, Bax/Bcl-2 ratio, caspase-3 activity) and DDRs (activation and levels of ATM, checkpoint kinase 2, Mdm2, ARF, and p53) were determined. Results: H. pylori induced apoptosis by increasing apoptotic indices and ROS levels. H. pylori activated DDRs (increased p-ATM, p-checkpoint kinase 2, ARF, p-p53, and p53, but decreased Mdm2) in gastric epithelial cells. KRG reduced ROS and inhibited increase in apoptotic indices and DDRs in H. pylori-infected gastric epithelial cells. KU-55933 suppressed DDRs and apoptosis in H. pylori-infected gastric epithelial cells, similar to KRG. Conclusion: KRG suppressed ATM-mediated DDRs and apoptosis by reducing ROS in H. pylori-infected gastric epithelial cells. Supplementation with KRG may prevent the oxidative stress-mediated gastric impairment associated with H. pylori infection.