• Journal of Korean Society of Environmental Engineers
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• v.27 no.9
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• pp.1006-1015
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• 2005

We investigated the effect of hydroxyl radicals on the photolysis of triclosan (TCS), which is a potent broad-spectrum antimicrobial agent. TCS degradation during the initial reaction time of 5 min followed a pseudo-first order kinetic model ai all light intensities at a wavelength of 365 nm and at the low light intensities at a wavelength of 254 nm. The photodegradation rate significantly increased with decreasing wavelength and increasing the UV intensities. The activity of hydroxyl radicals was suppressed when methanol was used as the solvent instead of water. An increase in the photon effect was observed when the UV intensity was higher than $5.77{\times}10^{-5}$ einstein $L^{-1}min^{-1}$ at 254 nm, and lower than $1.56{\times}10^{-4}$ einstein $L^{-1}min^{-1}$ at 365 nm. The quantum yield efficiency for the photolysis of TCS was higher at 365 nm than at 254 nm among the above mentioned UV intensities. Dibenzodichloro-p-dioxin (DCDD) and dibenzo-p-dioxin were detected as intermediates at both UV intensities of $1.37{\times}10^{-4}$ and $1.56{\times}10^{-4}$ einstein $L^{-1}min^{-1}$ at 365 nm. Dichlorophenol and phenol were also detected in all cases. Based on our findings, we presented a possible mechanism of TCS photolysis.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.