• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.370-371
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• 2011

This paper presents a control algorithm that minimizes the DC-link capacitance by decreasing the capacitor current. The capacitor current can be nullified by a feedback compensation term which is calculated from the power balance in the AC/DC converter. As a result, voltage variation in the DC-link is reduced further, which makes a large reduction in the size of DC-link capacitors which are expensive and have limitations in life time. Simulations are performed with two 80uF DC-link capacitors, which can be replaced by film capacitors.

• Journal of Power Electronics
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• v.17 no.3
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• pp.664-673
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• 2017

With the development of multilevel converters, cascaded single-phase H-bridge rectifiers (CHBRs) has become widely adopted in high-voltage high-power applications. In this study, sequence pulse modulation (SPM) is proposed for CHBRs. SPM is designed to balance the dc-link voltage and maintain the smooth changes of switch states. In contrast to phase disposition modulation, SPM balances the dc-link voltage even after removing the load of one submodule. The operation principle of SPM is deduced, and the unbalance degree of SPM is analyzed. All the proposed approaches are experimentally verified through a prototype of a four-module (nine-level) CHBR. Conclusions are drawn in accordance with the results of SPM and its imbalance degree analysis.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1315-1324
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• 2018

A novel three-phase four-wire inverter topology is presented in this paper. This topology is equipped with a special capacitor balance grid without magnetic saturation. In response to unbalanced load and unequal split DC-link capacitors problems, a qusi-full-bridge DC/DC topology is applied in the balance grid. By using a high-frequency transformer, the energy transfer within the two split dc-link capacitors is realized. The novel topology makes the voltage across two split dc-link capacitors balanced so that the neutral point voltage ripple is inhibited. Under the condition of a stable neutral point voltage, the three-phase four-wire inverter can be equivalent to three independent single phase inverters. As a result, the three-phase inverter can produce symmetrical voltage waves with an unbalanced load. To avoid forward transformer magnetic saturation, the voltages of the primary and secondary windings are controlled to reverse once during each switching period. Furthermore, an improved mode chosen operating principle for this novel topology is designed and analyzed in detail. The simulated results verified the feasibility of this topology and an experimental inverter has been built to test the power quality produced by this topology. Finally, simulation results verify that the novel topology can effectively improve the inhibition of an inverter with a three-phase unbalanced load while decreasing the value of the split capacitor.

• Journal of Power Electronics
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• v.19 no.2
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• pp.487-496
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• 2019

For a solid-state transformer (SST), some factors, such as signal delay, switching loss and differences in the system parameters, lead to unbalanced DC-link voltages among the cascaded H-bridges (CHB). With a control method implemented in the ${\alpha}{\beta}$ frame, the DC-link voltages are balanced, and the reactive power is equally distributed among all of the H-bridges. Based on the ${\alpha}{\beta}$ frame control, the system can achieve independent active current and reactive current control. In addition, the control method of the high-voltage stage is easy to implement without decoupling or a phase-locked loop. Furthermore, the method can eliminate additional current delays during transients and get the dynamic response rapidly without an imaginary current component. In order to carry out the controller design, the vector refactoring relations that are used to balance DC-link voltages are derived. Different strategies are discussed and simulated under the unbalanced load condition. Finally, a three-cell CHB rectifier is constructed to conduct further research, and the steady and transient experimental results verify the effectiveness and correctness of the proposed method.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.3
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• pp.205-213
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• 2021

Due to the advantage of reducing the voltage applied to the switch semiconductor, the input series and output parallel combination is widely used in systems with high input voltage and large output current. On the other hand, the LLC converter is widely used as a high-efficiency power converter, and when connected by ISOP combination, there is a possibility that input voltage imbalance may occur due to a mismatch of passive devices. To avoid damaging the switching device, this study analyzed the DC-link voltage imbalance of a high-capacity supply using an ISOP LLC converter. In addition, the case where DC-link unbalance control was applied and the case not applied was analyzed respectively. Based on this analysis, an initial start-up algorithm was proposed to prevent input power semiconductor device damage due to DC-link over-voltage. The effectiveness of the proposed algorithm has been verified through simulations and experiments.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1486-1495
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• 2019

Dealing with the DC link fault poses a technical problem for an HVDC based on a modular multilevel converter. The fault suppressing mechanisms of several sub-module topologies with DC fault current blocking capacity are examined in this paper. An improved half-bridge sub-module topology with double direction control switch is also designed to address the additional power consumption problem, and a sub-module topology called hybrid double direction blocking sub module (HDDBSM) is proposed. The DC fault suppression characteristics and sub-module capacitor voltage balance problem is also analyzed, and a self-startup method is designed according to the number of capacitors. The simulation model in PSCAD/EMTDC is built to verify the self-startup process and the DC link fault suppression features.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.95-101
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• 2017

A simple and practical voltage balance method for a solid-state transformer (SST) is proposed to reduce the voltage difference of cascaded H-bridge converters. The tolerance device components in SST cause the imbalance problem of DC-link voltage in the H-bridge converter. The Max/Min algorithms of voltage balance controller are merged in the controller of an AC/DC rectifier to reduce the voltage difference. The DC-link voltage through each H-bridge converter can be balanced with the proposed control methods. The design and performance of the proposed SST are verified by experimental results using a 30 kW prototype.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1178-1188
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• 2014

This study proposes a finite-state model predictive controller to regulate the load current and balance the DC-link capacitor voltages of a four-leg neutral-point-clamped converter. The discrete-time model of the converter, DC-link, inductive filter, and load is used to predict the future behavior of the load currents and the DC-link capacitor voltages for all possible switching states. The switching state that minimizes the cost function is selected and directly applied to the converter. The cost function is defined to minimize the error between the predicted load currents and their references, as well as to balance the DC-link capacitor voltages. Moreover, the current regulation performance is improved by using a two-step prediction horizon. The feasibility of the proposed predictive control scheme for different references and loads is verified through real-time implementation on the basis of dSPACEDS1103.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.117-120
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• 1993

In this paper, a novel DC link voltage control scheme for a single-phase PWM converter is proposed. The main idea of the control scheme is eliminating the effect of dc link voltage harmonics by using power balance of input side and output side. With the proposed strategy, faster transient response than that of conventional method using low-pass filter can be obtained. In addition, a half period current control, based at equal switching frequency, is proposed. The validity of the proposed scheme is verified by simulation results for GTO PWM converter system.

• Journal of Power Electronics
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• v.17 no.3
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• pp.653-663
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• 2017

Multilevel active neutral-point-clamped (ANPC) converter combines the advantages of three-level ANPC converter and multilevel flying capacitor (FC) converter. However, multilevel ANPC converter often suffers from capacitor voltage balancing problems. In order to solve the capacitor voltage balancing problems for five-level ANPC converter, phase-shifted pulse width modulation (PS-PWM) is used, which generally provides natural voltage balancing ability. However, the natural voltage balancing ability depends on the load conditions and converter parameters. In order to eliminate voltage deviations under steady-state and dynamic conditions, the active voltage-balancing control (AVBC) methods of floating capacitors and dc-link capacitors based on PS-PWM are proposed. First, the neutral-point current is regulated to balance the neutral-point voltage by injecting zero-sequence voltage. After that, the duty cycles of the redundant switch combinations are adjusted to balance the floating-capacitor voltages by introducing moderating variables for each of the phases. Finally, the effectiveness of the proposed AVBC methods is verified by experimental results.