• The Transactions of the Korean Institute of Power Electronics
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• v.2 no.1
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• pp.33-38
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• 1997

Generally, various semiconductor switching devices for power systems are used in battery chargers for electric vehicle. When these used, it takes the problems of transient-current or distortion of waveforms in power systems near by battery chargers because of harmonics and large peak-current, low power factor, etc., caused by the non-linearity of these devices. Recently, power factor control, line current peak-cut, harmonics reduction which was ignored in past is more and more important. In this paper, to solve those problems we will improve the characteristics of voltage rising and propose the high power factor converter circuit for battery chargers. Our proposed system convert commutated voltage to AC resonant wave in high frequency inverter and rectify the link voltages passed high-frequency transformer and transfer the DC voltages. Especially, the effect using these converter system can be improved very large by power factor control and we have to verify the possibilities of improvement through the experiment of Pb-Acid battery application.

• Journal of Power Electronics
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• v.15 no.1
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• pp.190-201
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• 2015

This paper uses the switching function approach to present a simple state model of the Vienna-type rectifier. The approach introduces the relationship between the DC-link neutral point voltage and the AC side phase currents. A novel direct power control (DPC) strategy, which is based on the sliding mode control (SMC) for Vienna I rectifiers, is developed using the proposed power model in the stationary ${\alpha}-{\beta}$ reference frames. The SMC-based DPC methodology directly regulates instantaneous active and reactive powers without transforming to a synchronous rotating coordinate reference frame or a tracking phase angle of grid voltage. Moreover, the required rectifier control voltages are directly calculated by utilizing the non-linear SMC scheme. Theoretically, active and reactive power flows are controlled without ripple or cross coupling. Furthermore, the fixed-switching frequency is obtained by employing the simplified space vector modulation (SVM). SVM solves the complicated designing problem of the AC harmonic filter. The simplified SVM is based on the simplification of the space vector diagram of a three-level converter into that of a two-level converter. The dwelling time calculation and switching sequence selection are easily implemented like those in the conventional two-level rectifier. Replacing the current control loops with power control loops simplifies the system design and enhances the transient performance. The simulation models in MATLAB/Simulink and the digital signal processor-controlled 1.5 kW Vienna-type rectifier are used to verify the fast responses and robustness of the proposed control scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.213-218
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• 2020

In this study, we propose a control algorithm to reduce the unbalanced characteristics of a three-phase system power caused by the unbalanced load of the AC electric railway. Then, we verify its performance through the design of a power compensator and experiments applying it. Like electric railway systems, a Scott transformer is applied, and the load and single-phase back-to-back converters are connected to the M-phase and T-phase outputs. The back-to-back converter monitors the difference in active power between the unbalanced loads in real-time and compensates for the power by using bidirectional characteristics. The active power is performed through PI control in the synchronous coordinate system, and DC link overall voltage and voltage balancing control are controlled jointly by M-phase and T-phase converters to improve the responsiveness of the system. To verify the performance of the proposed power compensation device, an experiment was performed under the condition that M-phase 5 kW and T-phase 1 kW unbalanced load. As a result of the experiment, the unbalance rate of the three-phase current after the operation of the power compensator decreases by 58.66% from 65.04% to 6.38%, and the excellent performance of the power compensator proposed in this study is verified.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.5
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• pp.438-445
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• 2001

This paper presents a high frequency modulation electronic ballast for the metal halide lamp. As the proposed ballast operates in high frequency ranges and can start up the lamp using the LC resonant circuit without external igniter, the proposed ballast is very compact and has a good efficiency in comparison with the conventional low frequency electronic ballast. The proposed ballast is controlled with the modulated frequency in the range of 20kHz to 100kHz in order to avoid the acoustic resonance phenomenon. In this paper, a new realtime acoustic resonance detection method is proposed to evaluate the characteristics of the ballast. The no load protection algorithm and power control algorithm through the detection of the DC link current are described. Finally, the experimental results on the proto-type ballast of 150w metal halide lamp with the proposed methods are discussed.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.2
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• pp.115-122
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• 2007

In this paper, a novel fault detection method for fault tolerant control is proposed when the NPC inverter has a open failure in the switching device. The open fault of switching device is detected by checking the variation of a leg-voltage in the neutral-point-clamped inverter and the two phases control method is used for continuously balance the three phases voltage to the load. It can be achieve the fault tolerant control for improving the reliability of the NPC inverter by the fault detection and reconfiguration. This method has fast detection ability and a simple realization for fault detection, compared with a conventional method. Also, this fast detection ability improved the harmful effects such as DC-link voltage unbalance and overstress to other switching devices from a delay of fault detection. The proposed method has been verified by simulation and experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.1
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• pp.11-19
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• 2011

This paper describe development of a hardware simulator for the DFIG wind power system, which was designed considering wind characteristic, blade characteristic, and blade inertia compensation. The simulator consists of three major parts, such as wind turbine model using induction motor, doubly-fed induction generator, converter-inverter set. and control system. The turbine simulator generates torque and speed signals for a specific wind turbine with respect to the given wind speed which is detected by Anemometer. This torque and speed signals are scaled down to fit the input of 3.5kW DFIG. The MSC operates to track the maximum power point, and the GSC controls the active and reactive power supplied to the grid. The operational feasibility was verified through computer simulations with PSCAD/EMTDC. And the implementation feasibility was confirmed through experimental works with a hardware set-up.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.401-408
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• 2012

A simple on-line elimination strategy of the dead time and inverter nonlinearity using the current slope information is presented for a PWM inverter-fed IPMSM (Interior Permanent Magnet Synchronous Motor) drive. In a PWM inverter-fed IPMSM drive, a dead time is inserted to prevent a breakdown of switching device. This distorts the inverter output voltage, resulting in a current distortion and torque ripple. In addition to the dead time, inverter nonlinearity exists in switching devices of the PWM inverter, which is generally dependent on operating conditions such as the temperature, DC link voltage, and current. The proposed scheme is based on the fact that the d-axis current ripple is mainly caused by the dead time and inverter nonlinearity. To eliminate such an influence, the current slope information is determined. The obtained current slope information is processed by the PI controller to estimate the disturbance caused by the dead time and inverter nonlinearity. The overall system is implemented using DSP TMS320F28335 and the validity of the proposed algorithm is verified through the simulation and experiments. Without requiring any additional hardware, the proposed scheme can effectively eliminate the dead time and inverter nonlinearity even in the presence of the parameter uncertainty.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Korean Society for information Management
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• v.17 no.4
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• pp.207-227
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• 2000

Recenily, major internalional STM(Science, Trchnical, and Mcdivine) Publichers have been developing prototype systems that can provide the refeence linking of jouinal articles within the scholarly literature on a cross-publisher basis using the URN(Universal Resouree Name). In Korea, it is hard to find the efforts to link the scattered digitalized documents to an individual user through a unified web. In this study, a linking model for an inergrated gatewny fro, bibliographic information to full tcxt has been desugned and 'Electronic Research Resourced Linking system (E3R/LS)' has been developed as a prototype for centralized static reference linking system. There are three major components for constructing refrernce linking systems. The firsl componcnt the Digital Object Identifiet(DO1). is introduced as the public identifier inrended to be applied wherever thr item needs to be identified. For denl~iymg Korean journal articles, llie extended SICI(Serlal Ilem and Conlribut~on Idealifier) has becn newly dehed in 1111s study and is used as a suiiia on DOI. The reierence datubasc conlams the second com~onenl, metadiltil, linkcd to implemenied by all information providers. The CnRI resolution system is used for resolving a DOI into a URL as the third component.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.188-188
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• 2000

DLC (Diamond-Like Carbon) 박막은 높은 경도와 가시광선 및 적외선 영역에서의 광 투과도, 전기적 절연성, 화학적 안정성 및 저마찰.내마모 특성 등의 우수한 물리.화학적인 물성을 갖고 있기 때문에 여러 분야의 응용연구가 이루어지고 있다. 이러한 DLC 박막을 제작하는 과정에는 여러 가지가 있으나, 본 연구에서는 ECR-PECVD electron cyclotron resonance plasma enhanced chemical vapor deposition) 방법을 사용하였다. 이것은 최근에 많이 이용되고 있는 방법으로, 이온화률이 높을뿐만 아니라 상온에서도 성막이 가능하고 넓은 진공도 영역에서 플라즈마 공정이 가능한 장점이 있다. 기판으로는 4" 크기의 S(100)를 사용하였고, 박막을 제작하기 전에 진공 중에서 플라즈마 전처리를 하였다. 플라즈마 전처리는 Ar 가스를 150SCCM 주입시켜 5$\times$10-1 torr 의 진공도를 유지시키면서, ECR power를 700W로 고정하고, 기판 bias 전압을 -300 V로 하여 5분 동안 기판을 청정하였다. DLC 박막은 ECR power를 700W. 가스혼합비와 유량을 CH4/H2 : 10/100 SCCM, 증착시간을 2시간으로 고정하고, 기판 bias 전압을 0, -50, -75, -100, -150, -200V로 변화시켜가면서 제작하였다. 이때 ECR 소스로부터 기판까지의 거리는 150mm로 하였고, 진공도는 2$\times$10-2torr 였으며, 기판 bias 전압은 기판에 13.56 MHz의 RF power를 연결하여 RF power에 의해서 유도되는 negative DC self bias 전압을 이용하였다. 제작된 박막을 Auger electron spectroscopy, elastic recoil detection, Rutherford backscattering spectroscopy, X-ray diffraction, secondary electron microscopy, atomic force microscoy, $\alpha$-step, Raman scattering spectroscopu, Fourier transform infrared spectroscopy 및 micro hardness tester를 이용하여 기판 bias 전압이 DLC 박막의 특성에 미치는 영향을 조사하였다. 분석결과 본 연구에서 제작된 DLC 박막은 탄소와 수소만으로 구성되어 있으며, 비정질 상태임을 알 수 있었다. 기판 bias 전압의 증가에 따라 박막의 두께가 감소됨을 알 수 있었고, -150V에서는 박막이 거의 만들어지지 않았으며, -200V에서는 기판 표면이 식각되었다. 이것은 기판 bias 전압과 ECR 플라즈마에 의한 이온충돌 효과 때문으로 판단되며, 150V 이하에서는 증착되는 양보다 re-sputtering 되는 양이 더 많을 것으로 생각된다. 기판 bias 전압을 증가시킬수록 플라즈마에 의한 이온충돌 현상이 두드러져 탄소와 결합하고 있던 수소원자들이 떨어져 나가는 탈수소화 (dehydrogenation) 현상을 확인할 수 있었으며, 이것은 C-H 결합에너지가 C-C 결합이나 C=C 결합보다 약하여 수소 원자가 비교적 해리가 잘되므로 이러한 현상이 일어난다고 판단된다. 결합이 끊어진 탄소 원자들은 다른 탄소원자들과 결합하여 3차원적 cross-link를 형성시켜 나가면서 내부 압축응력을 증가시키는 것으로 알려져 있으며, hardness 시험 결과로 이것을 확인할 수 있었다. 그리고 표면거칠기는 기판 bias 전압을 증가시킬수록 더 smooth 해짐을 확인하였다.인하였다.