• 제목/요약/키워드: DC-DC 변환기

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Efficient Intra Prediction Mode Decision Using DCT Coefficients for the Conversion of MPEG-2 to H.264 Standard in Ubiquitous Communication Environment (유비쿼터스 통신 환경에서 MPEG-2의 H.264로의 Transcoding 과점에서 DCT 계수를 이용한 효율적인 인트라 예측 모드 결정 기법)

  • Kim, Yong-Jae;Lee, Chang-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.9C
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    • pp.697-703
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    • 2008
  • The H.264/AVC video coding standard provides higher coding efnciency compared to the conventional MPEG-2 standard. Since a lot of videos have been encoded using MPEG-2, the format conversion from MPEG-2 to H.264 is essential. In this paper, we propose an efficient method for the conversion of DCT coefficients to H.264/AVC transform coefficients. This conversion is essential, since $8{\times}8$ DCT and $4{\times}4$ integer transform are used in MPEG-2 and H.264/AVC, respectively. The mathematical analysis and computer simulation show that the computational complexity of the proposed algorithm is reduced compared to the conventional algorithm, while the loss caused by the conversion is negligible.

A Study on the Implementation of Inverter Systems for Regenerated Power Control (회생전력 제어용 인버터 시스템의 구현에 관한 연구)

  • 金 敬 源;徐 永 泯;洪 淳 瓚
    • The Transactions of the Korean Institute of Power Electronics
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    • v.7 no.2
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    • pp.205-213
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    • 2002
  • This paper deals with the implementation of three-phase VSI systems which can control the power regenerated from DC bus line to AC supply. The overall system consists of the line-to-line voltage and line current sensors, an actual power calculator using d-q transformation method, a complex power controller with PI control scheme, a gating signal generator for modified q-conduction mode, a DPLL for frequency followup, and Power circuits. Control board is constructed by using a 32-bit DSP TMS32C32, two EFLDs , six ADCs, and a DAC. To verify the performance of the proposed system, we designed and constructed the propotype with the power rating of 5kVA at AC 220V. Experimental results show that the regenerated active power is well controlled to its command vague and the regenerated reactive power still remained at nearly zero through all operating modes.

Implementation and Design of Wideband IFIU using Aperture Open Loop Resonator and Reversed Phase Technique (역 위상 기법과 Aperture를 갖는 개방형 루프 공진기를 사용한 광대역 IF 모듈 설계 및 제작)

  • 김영완
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.11
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    • pp.17-23
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    • 2004
  • The implementation and design of the wideband IFIU using aperture open loop resonator and reversed phase technique to reduce the local oscillator leakage signal was represented in this paper. The local oscillator leakage signal is generated in stage of frequency conversion, especially in frequency conversion of fully digital modulation signal close to DC signal. The leakage signal and spurious signals, which have effects on adjacent channel or in-band channel as interference signals, were reduced below -60 dBc for 45 Mbps and 155 Mbps IF interface units. The group delay for both IFIUs shows low ripple characteristics of 15 ns and 8 ns, respectively. Also, the amplitude ripple characteristic in 150 MHz bandwidth with L-band center frequency satisfies the required specification of 2 dB. The implemented IFIU provides the required specifications for wideband satellite communication system.

Low power 3rd order single loop 16bit 96kHz Sigma-delta ADC for mobile audio applications. (모바일 오디오용 저 전압 3 차 단일루프 16bit 96kHz 시그마 델타 ADC)

  • Kim, Hyung-Rae;Park, Sang-Hune;Jang, Young-Chan;Jung, Sun-Y;Kim, Ted;Park, Hong-June
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.777-780
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    • 2005
  • 모바일 오디오 적용을 위한 저전력 ${\Sigma}{\Delta}$ Modulator 에 대한 설계와 layout 을 보였다. 전체 구조는 3 차 단일 피드백 루프이며, 해상도는 16bit 을 갖는다. 샘플링 주파수에 따른 Over-sampling Ratio 는 128(46kHz) 또는 64(96kHz) 가 되도록 하였다. 차동 구조를 사용한 3 차 ${\Sigma}{\Delta}$ modulator 내의 적분기에 사용된 Op-Amp 는 DC-Gain 을 높이기 위해서 Gain-boosting 기법이 적용되었다. ${\Sigma}{\Delta}$ modulator 의 기준 전압은 전류 모드 Band-Gap Reference 회로에서 공급이 되며, PVT(Process, Voltage, Temperature) 변화에 따른 기준 전압의 편차를 보정하기 위하여, binary 3bit 으로 선택하도록 하였다. DAC 에서 사용되는 단위 커패시터의 mismatch 에 의한 성능 감소를 막기 위해, DAC 신호의 경로를 임의적으로 바꿔주는 scrambler 회로를 이용하였다. 4bit Quantizer 내부의 비교기 회로는 고해상도를 갖도록 설계하였고, 16bit thermometer code 에서 4bit binary code 변환시 발생하는 에러를 줄이기 위해 thermometer-to-gray, gray-to-binary 인코딩 방법을 적용하였다. 0.18um CMOS standard logic 공정 내 thick oxide transistor(3.3V supply) 공정을 이용하였다. 입력 전압 범위는 2.2Vp-p,diff. 이며, Typical process, 3.3V supply, 50' C 시뮬레이션 조건에서 2Vpp,diff. 20kHz sine wave 를 입력으로 할 때 SNR 110dB, THD 는 -95dB 이상의 성능을 보였고, 전류 소모는 6.67mA 이다. 또한 전체 layout 크기는 가로 1100um, 세로 840um 이다.

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Study Of Millimeter-Wave Passive Imaging Sensor Using the Horn Array Antenna (혼 배열 안테나를 이용한 밀리미터파 수동 이미징 센서 연구)

  • Lim, Hyun-Jun;Chae, Yeon-Sik;Kim, Mi-Ra;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.2
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    • pp.74-79
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    • 2010
  • We have designed a millimeter-wave passive imaging sensor with multi-horn antenna array. Six horn array antenna is suggested that it is integrated into one housing, and this antenna is effectively configurated m space to assemble with LNA of WR-10 structure. Antenna is designed to have the peak gain of 17.5dBi at the center frequency of 94GHz, and the return loss of less than -25dB in W-band, and the small aperture size of $6mm{\times}9mm$ for antenna configuration with high resolution. LNA is designed to have total gain of more than 55dB and noise figure of less than 5dB for good sensitivity. We made a detector for DC output translation of millimeter-wave signal with zero bias Schottky diode. It is shown that good sensitivity of more than 500mV/mW.

A Design of LLC Resonant Controller IC in 0.35 um 2P3M BCD Process (0.35 um 2P3M BCD 공정을 이용한 LLC 공진 제어 IC 설계)

  • Cho, Hoo-Hyun;Hong, Seong-Wha;Han, Dae-Hoon;Cheon, Jeong-In;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.5
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    • pp.71-79
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    • 2010
  • This paper presents a design of a LLC resonant controller IC. LLC resonant controller IC controls the voltage of the 2nd side by adjusting frequency the input frequency of the external resonant circuit. The clock generator is integrated to provide the pulse to the resonant circuit and its frequency is controlled by the external resistor. Also, the frequency of the VCO is adjusted by the feedback voltage. The protection circuits such as UVLO(Under Voltage Lock Out), brown out, fault detector are implemented for the reliable and stable operation. The HVG, and LVG drivers can provide the high current and voltage to the IGBT. The designed LLC resonant controller IC is fabricated with the 0.35 um 2P3M BCD process. The overall die size is $1400um{\times}1450um$, and supply voltage is 5V, 15V.

Development of Planar Active Electronically Scanned Array(AESA) Radar Prototype for Airborne Fighter (항공기용 평면형 능동 전자주사식 위상 배열(AESA) 레이더 프로토 타입 개발)

  • Chong, Min-Kil;Kim, Dong-Yoon;Kim, Sang-Keun;Chon, Sang-Mi;Na, Hyung-Gi
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.12
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    • pp.1380-1393
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    • 2010
  • This paper presents a design, fabrication and the test results of planar active electronically scanned array(AESA) radar prototype for airborne fighter applications using transmit/receive(T/R) module hybrid technology. LIG Nex1 developed a AESA radar prototype to obtain key technologies for airborne fighter's radar. The AESA radar prototype consists of a radiating array, T/R modules, a RF manifold, distributed power supplies, beam controllers, compact receivers with ADC(Analog-to-Digital Converter), a liquid-cooling unit, and an appropriate structure. The AESA antenna has a 590 mm-diameter, active-element area capable of containing 536 T/R modules. Each module is located to provide a triangle grid with $14.7\;mm{\times}19.5\;mm$ spacing among T/R modules. The array dissipates 1,554 watts, with a DC input of 2,310 watts when operated at the maximum transmit duty factor. The AESA radar prototype was tested on near-field chamber and the results become equal in expected beam pattern, providing the accurate and flexible control of antenna beam steering and beam shaping.

A 2.4-GHz Dual-Mode CMOS Power Amplifier with a Bypass Structure Using Three-Port Transformer to Improve Efficiency (3-포드 변압기를 이용한 바이패스 구조를 적용하여 효율이 개선된 이중 모드 2.4-GHz CMOS 전력 증폭기)

  • Jang, Joseph;Yoo, Jinho;Lee, Milim;Park, Changkun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.23 no.6
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    • pp.719-725
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    • 2019
  • We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.

Implementation of a DSP Based Fuel Cell Hardware Simulator (DSP기반 연료전지 하드웨어 시뮬레이터 구현)

  • Oum, Jun-Hyun;Lim, Young-Cheol;Jung, Young-Gook
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.23 no.1
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    • pp.59-68
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    • 2009
  • Fuel cell generators as the distributed generation system with a few hundred watt$\sim$a few hundred kilowatt capacity, can supply the high quality electric power to user as compared with conventional large scale power plants. In this paper, PEMFC(polymer electrolyte membrane fuel cell) generator as micro-source is modelled by using PSIM simulation software and DSP based fuel cell hardware simulator based on the PSIM simulation model is implemented. The relation of fuel cell voltage and current(V-I curve) is linearized by first order function on the ohmic area in voltage-current curve of fuel cell. The implemented system is composed of a PEMFC hardware simulator, an isolated full bridge dc boost converter, and a 60[Hz] voltage source PWM inverter. The voltage-current-power(V-I-P) characteristics of the implemented fuel cell hardware simulator are verified in load variation and transient state and the 60[Hz] output voltage sinusoidal waveform of the PWM inverter is investigated under the resistance load and nonlinear diode load.

Development of High-Speed Elevator Drive System using Permanent-magnet Synchronous Motor (영구 자석형 동기 전동기를 이용한 고속 엘리베이터 구동 시스템 개발)

  • 류형민;김성준;설승기;권태석;김기수;심영석;석기룡
    • The Transactions of the Korean Institute of Power Electronics
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    • v.6 no.6
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    • pp.538-545
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    • 2001
  • In this paper a gearless drive system using a permanent-maget synchronous motor for high speed elevators is addressed. The application of permanent magnet synchronous motor to an elevator traction machine enables several improvements including higher efficiency better ride comfort smaller size and lighter weight and so on A PWM boost converter has been also adopted so that DC-link voltage regulation bi-directional power flow and controllable power factor with reduced input current harmonics are possible. To increase the reliability and performance of overall control system the unified control board which can include the car and group controller as well as PWN converter/inverter controller has been designed based on a DSP TMS320VV33. In addition the dynamic load simulator system has been developed so that the drive system of high speed elevator can be tested and evaluated without and limitation on ride distance. Some experimental results are given to verify the effectiveness of the developed system.

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