• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.374-375
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• 2011

This paper presents a method to determine parameters of BTB (back-to-back) converters in terms of the enhancement of interface flow margins. Interface flow margin is by definition a measure of how much active power can be transferred from the external areas to the study area with the fixed load demand, and it is mainly constrained by system voltage stability. BTB converters are controllable equipments with the active power flow through them, and its DC link in fact can divide the AC systems at the location and hence can reduce the fault current level. This paper first cals margin sensitivities at the nose point of F-V curves and formulates an optimization problem to update the BTB parameters to improve the margins. This procedure is repeated performed until the required margin enhancement is achieved.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.365-374
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• 1998

The SHE(Selected Harmonic Elimination) PWM scheme which eliminates specific lower order harmonics can generate h high quality output waveforms in 3-level PWM inverters. However. its application has limited since SHE switching a angles cannot be calculated on-line by a microprocessor-implemented control system. Based on off-line optimization. in which multiple SHE solutions were found and analysed for 2 to 5 switching angles per quarter in the 3-level SHE PWM pattern. this paper presents an algebraic algorithm for an ordinary microprocessor to calculate approximate SHE S switching angles on-line with such high resolution that it makes no practical difference between the accurate and the a approximate SHE switching angles. By employing the variable of the dc-link voltage Vdc' the proposed SHE PWM p pattern can ideally compensate the dc input fluctuation together with selected harmonics eliminated.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1305-1317
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• 2015

Distributed generation systems (DGSs) have been getting more and more attention in terms of renewable energy use and new generation technologies in the past decades. The self-excited induction generator (SEIG) occupies an important role in the area of energy conversion due to its low cost, robustness and simple control. Unlike synchronous generators, the SEIG has to absorb capacitive reactive power from the outer device aiming to stabilize the terminal voltage at load changes. This paper presents a novel static VAR compensator (SVC) called a magnetic energy recovery switch (MERS) to serve as a voltage controller in SEIG powered DGSs. In addition, many small scale SEIGs, instead of a single large one, are applied and devoted to promote the generation efficiency. To begin with, an expandable mathematic model based on a d-q equivalent circuit is created for parallel SEIGs. The control method of the MERS is further improved with the objective of broadening its operating range and restraining current harmonics by parameter optimization. A hybrid control strategy is developed by taking both of the stand-alone and grid-connected modes into consideration. Then simulation and experiments are carried out in the case of single and double SEIG(s) generation. Finally, the measurement results verify that the proposed DGS with SVC-MERS achieves a better stability and higher feasibility. The major advantages of the mentioned variable reactive power supplier, when compared to the STATCOM, include the adoption of a small DC capacitor, line frequency switching, simple control and less loss.

• Journal of Magnetics
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• v.13 no.2
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• pp.37-42
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• 2008

In this paper, design parameters of high Q (> 50), high current inductor for on-chip power module were optimized by 4 Xs 3 Ys DOE (Design of Experiment). Coil spacing, coil thickness, ferrite thickness, and permeability were assigned to Xs, and inductance (L) and Q factor at 10 MHz, and resonance frequency ($f_r$) were determined Ys. Effects of each X on the Ys were demonstrated and explained using known inductor theory. Multiple response optimizations were accomplished by three derived regression equations on the Ys. As a result, L of 125 nH, Q factor of 197.5, and $f_r$ of 316.3 MHz were obtained with coil space of $127\;{\mu}m$, Cu thickness of $67.8\;{\mu}m$, ferrite thickness of $130.3\;{\mu}m$, and permeability 156.5. Loss tan ${\delta}=0$ was assumed for the estimation. Accordingly, Q factor of about 60 is expected at tan ${\delta}=0.02$.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1348-1357
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• 2015

Under traditional unified power quality conditioner (UPQC) control, a UPQC series converter (SC) is mainly used to handle grid-side power quality problems while its parallel converter (PC) is mainly used to handle load-side power quality problems. The SC and PC are relatively independent. The SC is usually in standby mode and it only runs when the grid voltage abruptly changes. In this paper, novel UPQC coordinated control strategies are proposed which use the SC to share the reactive power compensation function of the PC especially without grid-side power quality problems. However, in some cases, there will be a circulating current between the SC and the PC, which will probably influence the compensation fashion, the compensation capacity, or the normal work of the UPQC. Through an active power circulation analysis, strategies with and without a circulating current are presented which fuses the reactive power allocation strategy of the SC and the PC, the composite control strategy of the SC and the compensation strategy of the DC storage unit. Both of the strategies effectively solve the SC long term idle problem, limit the influence of the circulating current, optimize all of the UPQC units and reduce the production cost. An analysis, along with simulation andexperimental results, is presented to verify the feasibility and effectiveness of the proposed control strategies.

• Journal of Sensor Science and Technology
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• v.27 no.4
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• pp.269-274
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• 2018

High-sensitivity signal-to-noise ratio (SNR) microphones are essentially required for a broad range of automatic speech recognition applications. Piezoelectric microphones have several advantages compared to conventional capacitor microphones including high stiffness and high SNR. In this study, we designed a new piezoelectric membrane structure by using the finite elements method (FEM) and an optimization technique to improve the sensitivity of the transducer, which has a high-quality AlN piezoelectric thin film. The simulation demonstrated that the sensitivity critically depends on the inner radius of the top electrode, the outer radius of the membrane, and the thickness of the piezoelectric film in the microphone. The optimized piezoelectric transducer structure showed a much higher sensitivity than that of the conventional piezoelectric transducer structure. This study provides a visible path to realize micro-scale high-sensitivity piezoelectric microphones that have a simple manufacturing process, wide range of frequency and low DC bias voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• Applied Chemistry for Engineering
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• v.31 no.3
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• pp.291-298
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• 2020

ZITO/Ag/ZITO multilayer transparent electrodes at room temperature on glass substrates were prepared using RF/DC magnetron sputtering. Transparent conductive films with a sheet resistance of 9.4 Ω/㎡ and a transmittance of 83.2% at 550 nm were obtained for the multilayer structure comprising ZITO/Ag/ZITO (100/8/42 nm). The sheet resistance and transmittance of ZITO/Ag/ZITO multilayer films meant that they would be highly applicable for use in polymer-dispersed liquid crystal (PDLC)-based smart windows due to the ability to effectively block infrared rays (heat rays) and thereby act as an energy-saving smart glass. Effects of the thickness of the PDLC layer and the intensity of ultraviolet light (UV) on electro-optical properties, photopolymerization kinetics, and morphologies of difunctional urethane acrylate-based PDLC systems were investigated using new transparent conducting electrodes. A PDLC cell photo-cured using UV at an intensity of 2.0 mW/c㎡ with a 15 ㎛-thick PDLC layer showed outstanding off-state opacity, good on-state transmittance, and favorable driving voltage. Also, the PDLC-based smart window optimized in this study formed liquid crystal droplets with a favorable microstructure, having an average size range of 2~5 ㎛ for scattering light efficiently, which could contribute to its superior final performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.13-19
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• 2001

We report on the fabrication and characterization of $Al_{0.3}Ga_{0.7}N$ HFETs with different barrier layer thickness which were grown using plasma-assisted molecular beam epitaxy (PAMBE). The barrier thickness of $Al_{0.3}Ga_{0.7}N$/GaN HFETs could be optimized in order to maximize 2 dimensional electron gas induced by piezoelectric effect without the relaxation of $Al_{0.3}Ga_{0.7}N$ layer. $Al_{0.3}Ga_{0.7}N$/GaN (20 nm/2 mm) HFET with 0.6 ${\mu}m$-long and 34 ${\mu}m$-wide gate shows saturated current density ($V_{gs}=1\;V$) of 1.155 A/mm and transconductance of 250 ms/mm, respectively. From high frequency measurement, the fabricated $Al_{0.3}Ga_{0.7}N$/GaN HFETs showed $F_t=13$ GHz and $F_{max}=48$ GHz, respectively. The uniformity of less than 5% could be obtained over the 2 inch wafer. In addition to the optimization of epi-layer structure, the relation between breakdown voltage and high frequency characteristics has been examined.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.