• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.84-93
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• 2001

An electromagnetic micro x-y stage for probe-based data storage (PDS) has been fabricated. The x-y stage consists of a silicon body inside which planar copper coils are embedded, a glass substrate bonded to the silicon body, and eight permanent magnets. The dimensions of flexures and copper coils were determined to yield $100{\;}\mu\textrm{m}$ in x and y directions under 50 mA of supplied current and to have 440 Hz of natural frequency. For the application to PDS devices, electromagnetic stage should have flat top surface for the prevention of its interference with multi-probe array, and have coils with low resistance for low power consumption. In order to satisfy these design criteria, conducting planar copper coils have been electroplated within silicon trenches which have high aspect ratio ($5{\;}\mu\textrm{m}$in width and $30{\;}\mu\textrm{m}$in depth). Silicon flexures with a height of $250{\;}\mu\textrm{m}$ were fabricated by using inductively coupled plasma reactive ion etching (ICP-RIE). The characteristics of a fabricated electromagnetic stage were measured by using laser doppler vibrometer (LDV) and dynamic signal analyzer (DSA). The DC gain was $0.16{\;}\mu\textrm{m}/mA$ and the maximum displacement was $42{\;}\mu\textrm{m}$ at a current of 180 mA. The measured natural frequency of the lowest mode was 325 Hz. Compared with the designed values, the lower natural frequency and DC gain of the fabricated device are due to the reverse-tapered ICP-RIE process and the incomplete assembly of the upper-sided permanent magnets for LDV measurements.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.

• Journal of Navigation and Port Research
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• v.27 no.5
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• pp.505-511
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• 2003

In this paper, a driving amplifier stage with 1 Watt output has been designed and fabricated, which is operating at UHF band( 470 ∼ 806 MHz) for digital TV repeater. In the driving amplifier stage, preamplifier and 1 Watt unit amplifier are integrated by one electric substrate which is 2.53 in dielectric constant and 0.8 mm thickness. When the driving amplifier stage is flown by bias voltage of 28 V DC and current of 900 mA. it has the gain of more than 53.5 dB. the gain flatness of $\pm$0.5 dB and return loss of less than -15 dB in 470 ∼ 806 MHz. Also, when two signals at 2 MHz frequency interval are input port into the driving amplifier stage with 1 Watt output, it resulted in excellent characteristics to designed specification with showing intermodulation distortion characteristics of more than 48 dBc.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.29-36
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• 2000

The principle and design of two-stage CMOS operational amplifier with rail-to-rail input and class-AB output stage is presented. The rail-to-rail input stage shows almost constant transconductance independent of the common mode input voltage range in global transistor operation region. This new technique does not make use of accurate current-voltage relationship of MOS transistors. Hence it was achieved by using simple linear relationship of currents. The simulated transconductance variation using SPICE is less the 4.3%. The proposed global two-stage opamp can operate both in strong inversion and in weak inversion. Class AB output stage proposed also has a full output voltage swing and a well-defined quiescent current that does not depend on power supply voltage. Since feedback class- AB control is used, it is expected that this output stage can be operating in extremely low voltage. The variation of DC-gain and unity-gain frequency is each 4.2% and 12%, respectively.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.152-159
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• 2004

In this study, we design the one-chip PWM IC with high voltage power switch (300V class LDMOSFET) for SMPS (Switching Mode Power Supply) application. Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain $({\simeq}65dB)$, unity frequency $({\simeq}190kHz)$ and large $PM(75^{\circ})$. comparator is designed with 2 stage. Saw tooth generators operate with 20kHz oscillation frequency. Also, we optimize drift concentration & drift length of n-LDMOSFET for design of high voltage switching device. It is shown that simulation results have the breakdown voltage of 350V. (using ISE-TCAD Simulation tool). PWM IC with power switching device is designed with 2um design rule and Bi-DMOS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.4
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• pp.542-551
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• 1998

In this study, a method of error compensation for channel gain imbalance, phase imbalance and local oscillator leakage in the modulator of frequency direct conversion is suggested. The compensation of channel imbalance can be carried out by using the received power after transmitting test signal. By applying this method, the phase imbalance conversion with frequency can be easily compensated since this method is rarely affected by the transmission channel. It is confirmed that the algorithm proposed in this study(iteration coefficient=11) converges faster than conventional algorithm(iteration coefficient=43). From the numerical results, the DC-offset, channel gain, phase imbalance compensation coefficient and iteration number converges into($f_1$=0.0199999, $f_2$=-0.050001, $C_{22}$=0.9133, $C_{12}$=-0.0524, N=13) when the local oscillator leakage is not considered. However, it converges into($f_1$=-0.02, $f_2$=-2.2476, $C_{22}$=0.9133, $C_{12}$=-0.0524, N=16) when the local oscillator leakage is considered.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.632-638
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• 2011

This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.

• Journal of IKEEE
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• v.20 no.3
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• pp.279-284
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• 2016

This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.

• Journal of Navigation and Port Research
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• v.26 no.2
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• pp.215-220
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• 2002

In this paper, the 100 watt unit ower amplifier using temperature independent biasing for DTV (Digital Television) repeater application is designed and fabricated. The DC operation point of this unit power amplifier at temperature variation from $20^{\circ}C$ to $100^{\circ}C$ is fixed by active bias circuit. The variation of current consumption in the 100 watt unit power amplifier has an excellent characteristics of less than 0.6A. The implemented unit power amplifier has the gain over 12dB, the gain flatness of less than 0.5dB and input and output return, loss of than 15dB over the DTV repeater frequency range (470~806MHz). This unit power amplifier yields intermodulation distortion(IMD) of more than 32dBc at 2MHz offset, which satisfies the IMD at output power of 100 watt (50dBm).

• Molecules and Cells
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• v.46 no.12
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• pp.746-756
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• 2023

A recent study revealed that the loss of Deup1 expression does not affect either centriole amplification or multicilia formation. Therefore, the deuterosome per se is not a platform for amplification of centrioles. In this study, we examine whether gain-of-function of Deup1 affects the development of multiciliated ependymal cells. Our time-lapse study reveals that deuterosomes with an average diameter of 300 nm have two different fates during ependymal differentiation. In the first instance, deuterosomes are scattered and gradually disappear as cells become multiciliated. In the second instance, deuterosomes self-organize into a larger aggregate, called a deuterosome cluster (DC). Unlike scattered deuterosomes, DCs possess centriole components primarily within their large structure. A characteristic of DC-containing cells is that they tend to become primary ciliated rather than multiciliated. Our in utero electroporation study shows that DCs in ependymal tissue are mostly observed at early postnatal stages, but are scarce at late postnatal stages, suggesting the presence of DC antagonists within the differentiating cells. Importantly, from our bead flow assay, ectopic expression of Deup1 significantly impairs cerebrospinal fluid flow. Furthermore, we show that expression of mouse Deup1 in Xenopus embryos has an inhibitory effect on differentiation of multiciliated cells in the epidermis. Taken together, we conclude that the DC formation of Deup1 in multiciliated cells inhibits production of multiple centrioles.