• Journal of Electrical Engineering and Technology
• /
• 제11권3호
• /
• pp.662-669
• /
• 2016

In this work, nonlinear control of a three-phase shunt active power filter (SAPF) has been studied and compared to classical control based on proportional integral regulator. The control strategy is based on the direct current method using sliding mode control (SMC), where the aim is to regulate the average voltage across the dc bus of the inverter. Details are given for the control algorithm; the controller is comprised of a current loop which utilizes a hysteresis controller to generate the gating signals for the switching devices, and a nonlinear controller based on SMC law which is different from classical laws based on error between reference and measured output voltage of the inverter. Sliding surface applied in this work contains the whole of state variables, in order to ensure full control of the system behavior in the presence of disturbances that affect the supply source, the load parameters or the reference value. The designed controller offers advantage that it can gives the improvement of dynamic and static performances in cases of large disturbances. A comparison of the effects of PI control and SMC on the APF response in steady stat, under line variations, load variations, and different component variations is performed.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
• /
• pp.648-653
• /
• 1998

The conventional three-phase rectifier with bulky LC output filter has been widely used in the industry because of its distinctive advantages over the active power factor correction rectifier such as simple circuit, high reliability, and low cost. Over than 0.9 power factor can be achieved, which is acceptable in most of industry applications. This rectifier, however, is not easy to use for high power density applications since the LC filter is bulky and heavy. To solve this problem, a new simple rectifier is presented in this paper. By eliminating the bulky LC filter from the conventional diode rectifier without losing most of the advantages of the conventional rectifier, very high power density power conversion with high power factor can be achieved. Operation principle and design considerations are illustrated and verified by Pspice simulation and experimental results from a prototype of 3.3 kW rectifier followed by 100KHz zero voltage switching full bridge PWM converter

• Journal of Electrical Engineering and Technology
• /
• 제10권5호
• /
• pp.2018-2030
• /
• 2015

A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal reference-random carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA).

• 전기학회논문지
• /
• 제62권11호
• /
• pp.1628-1632
• /
• 2013

HEP(Head Electric Power) system, supplying 3-phase service power to the coach vehicles, is a kind of special auxiliary power equipment which is boarded on 8200 series electric locomotives in KORAIL. This equipment shares high voltage DC link with a main propulsion converter/inverter systems. It was difficult to use high frequency PWM technique so that GTO has been used as a power device same like the main power system. Due to low PWM frequency(300Hz) of HEP inverter, the output voltage has less power quality comparing to normal SIV(Static Inverter) system. In this paper, an optimal PWM strategy is presented for new IGBT type HEP inverter system. Several PWM techniques were investigated to improve output voltage quality under fixed lower filter inductance and not high PWM frequency. Finally PC simulations have been done to clarify its availability.

• 한국산학기술학회논문지
• /
• 제20권3호
• /
• pp.491-499
• /
• 2019

최근에, 전원 공급 장치에 있어서 파워의 품질에 대한 요구가 높아지고 있다. IEC 61000-3-2 규격은 조명을 위한 AC/DC 전원 공급 장치에 대하여 역률(PF)과 전체 파형 왜곡률(THD)에 대한 규격을 만족하도록 요구하고 있다. 또 출력단의 전류 변화에 의해 발광체 광량이 바뀜에 따라 발생되는 플리커 현상에 대해 유럽권 선진국가는 ripple rate의 기준을 15~30%로 설정해 규제하고 있다. 따라서 국내에서도 기준을 마련하고 규제를 추진 중에 있다. 그래서 본 논문은 PFC 규격을 만족하고, 회로 1차, 2차 간 절연 기능을 가지기 위해 Flyback 컨버터를 적용하며, LED 전류의 저주파 리플을 저감하기 위해 Flyback, Coupled Inductor, LC 병렬 공진 필터, LLC 공진 필터, Cuk을 이용한 각각의 LED 구동회로를 PSIM을 통해 시뮬레이션 함으로써 각각의 방식들을 비교하였으며, 출력측 리플 저감을 위해 1차측에 Coupled Inductor와 2차측에 LC 공진을 적용한 Coupled LC 공진 회로를 제안하였으며, Coupled LC 공진 방식은 출력 커패시터가 78uF으로 작으며, 출력 리플은 전압 2.38V, 전류 0.05A로 기존의 방식보다 22%의 출력 리플 저감을 확인 하였다.

• Journal of electromagnetic engineering and science
• /
• 제10권1호
• /
• pp.28-34
• /
• 2010

This paper introduces a new U.S. ultra-wideband(UWB: 3.1~10.6 GHz) 1:2 power divider based on a single section Wilkinson type configuration. The divider provides very flat in-band power splitting, high isolation, low insertion loss, sharp roll-off bandpass filtering, and DC blocking characteristics. The circuit consists of a $\lambda$/4 Y resonator, three capacitively coupled $\lambda$/2 short-circuited lines, and a resistor between the two output ports. The circuit structure was simulated with ADS and HFSS, and realized with low-temperature co-fired ceramic(LTCC) green tape, which has a dielectric constant of 7.8. $|S_{11}|$ better than 10 dB, $|S_{21}|$ and $|S_{31}|$ less than 3.2 dB, with both $|S_{22}|$ and $|S_{32}|$ measured as better than 12 dB for the whole UWB band. Measurement results agree closely with HFSS simulation results. The power divider has a compact size of $4\times9\times0.6mm^3$.

• Journal of Power Electronics
• /
• 제17권5호
• /
• pp.1363-1371
• /
• 2017

In this paper, an improved Direct Power Control (DPC) algorithm is presented for grid connected three phase PWM rectifiers. The new DPC approach is based on two main tasks. First the optimization of the look-up table, which is well-known in conventional DPC, is outlined for selecting the optimum converter output voltage vectors. Secondly a very simple and effective method is used to directly calculate their duty cycles from the power errors. Therefore, the measured active and reactive powers are made to track their references using hysteresis controllers. Then two vectors are selected and applied during one control cycle to minimize both the active and reactive power ripples. The main advantages of this method are that there is no need of linear current controllers, coordinates transformations or modulators. In addition, the control strategy is able to operate at constant switching frequencies to ease the design of the power converter and the AC harmonic filter. The control exhibits a good steady state performance and improves the dynamic response without any overshoot in the line current. Theoretical principles of the proposed method are discussed. Both simulation and experimental results are presented to verify the performance and effectiveness of this control scheme.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
• /
• 제55권8호
• /
• pp.389-395
• /
• 2006

In the single-phase switched reluctance motor (SRM) drive, the required DC source is generally supplied by the circuit consisting of bridge rectifier with diodes and many filter capacitances connected with AC source. Although the peak torque ripple of SRM is small because of large capacity of the capacitance, the charge and discharge time swhich the AC source acts on the capacitance are small and the peak current will pass on the side of source, so power factor and system efficiency decrease. Therefore a novel SRM drive system is presented in this paper, which includes drive circuit realizing reduction of torque ripple and improvement of power factor and switching topology. The proposed drive circuit consists of one switching part and diodes which can separate the output of AC/DC rectifier from the large capacitance and supply power to SRM alternately in order to realize reduction of torque ripple and improvement of power factor through the turn on and turn off of switching part. In addition, the validity of method is tested by simulation and experiment.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
• /
• pp.998-999
• /
• 2006

포항가속기 연구소의 선형가속기에는 22개의 솔레노이드 전자석, 16개의 사극전자석 그리고 전자빔의 궤도 조절을 위한 16개의 2극 전자석이 있다. 선형가속기의 빔을 저장링으로 공급해주는 빔 전송선에는 22개의 사극전자석과 13개의 빔 궤도 조절용 이극 전자석이 있다. 전자빔의 정밀 제어를 위하여 전자석의 전원장치는 출력전류 분해능은 16bit 이상이고 출력전류의 안정도는 최대출력에 대하여 ${\pm}50ppm$ 이하의 고정밀 고안정도가 요구된다. 이를 위하여 풀-브릿지 4상한 DC/DC 컨버터를 이용한 전자석전원장치를 개발 하였다. 전원장치의 입력전압 직류 40V이고 출력전류는 단방향 전원장치는 최대 50A/50V 이고 양방향 전원장치는 ${\pm}20A/20V$이다. 스위칭 주파수는 50 kHz이다. 전원장치의 출력부에 필터가 없으면 출력전류에는 스윗칭과 관련된 주파수 성분이 포함 되고 전자빔은 이들 주파수 성분에 대하여 영향을 받게 된다. 이러한 이유로 출력 필터의 cut-off 주파수는 5 kHz 이하가 되어야 한다. 본 논문에서는 고정밀 고안정 스윗칭 전자석전원장치를 위한 출력필터의 설계, 제작 그리고 이를 적용한 전자석전원장치에 대하여 논의 하고자 한다.

• 한국전자파학회논문지
• /
• 제8권1호
• /
• pp.52-60
• /
• 1997

MPIE 수치해석적 기법과 초고주파대 CAD 소프트웨 어 인 EEsof를 활용하여 2단 23 GHz대 저잡음 증폭기를 설계하였다 이 회로는 먼저 EEsof를 이용하여 기초 설계를 하고 MPIE 기볍에 의해 수정과 상세 해석을 실시 하는 방법으로 하였다. 입.출력단의 정합 부분은 평행 결합 여파기 형태로 하였는데 이는 임피던스 정합과 DC 차단을 동시에 실시할 수 있을 뿐만 아니라 불연속 부분이 적고 설계시 해석의 오차가 적은 장점을 가지고 있다. FET칩은 접지 급속 변에서 직접 부착하였다. 제작된 증폭기는 이득이 콘넥터 손실 1.8 dB를 고려하지 않은 상태에서 15.2 dB, 잡음지수가 2.7 dB를 나타냈다. 이와 같은 결과는 본 논문에서 사용한 설계 기법과 정합 기술이 20 GHz대 이상의 회로설계 및 제작에 적합하다고 할 수 있다.