• Transactions of the Korean Society of Mechanical Engineers A
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• v.24 no.12
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• pp.2995-3002
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• 2000

The remaining life estimation for the aged components in power plants as well as chemical plants are very important beacuse mechanical properties of the components are degraded with time of service exposure in high temperature. Since it is difficult to take specimens from the operating components to evaluate mechanical properties of components nondestructive techniques are needed to estimate the degradation. In this study, test materials with 4 different degradation levels were prepared by isothermal aging heat treatment at 630$\^{C}$. And the DC potential drop method and destructive methods such as tensile, K(sub)IC and hardness tests were used in order to evaluate the degradation of 1-Cr-1Mo-0.25V steels. The objective of this study is to investigate the possibility of the application of DCPD method to estimated the material degradation, and to analyse the relationship between the electrical relationship between the electrical resistivity and the degree material degradation.

• ETRI Journal
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• v.40 no.6
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• pp.693-698
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• 2018

This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.

• Asian Pacific Journal of Cancer Prevention
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• v.14 no.11
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• pp.6363-6367
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• 2013

Atractylis lancea (Thunb.) DC. (AL), an important medicinal herb in Asia, has been shown to have anti-tumor effects on cancer cells, but the involved mechanisms are poorly understood. This study focused on potential effects and molecular mechanisms of AL on the proliferation of the Hep-G2 liver cancer cell line in vitro. Cell viability was assessed by MTT test in Hep-G2 cells incubated with an ethanol extract of AL. Then, the effects of AL on apoptosis and cell cycle progression were determined by flow cytometry. Telomeric repeat amplification protocol (TRAP) assays was performed to investigate telomerase activity. The mRNA and protein expression of human telomerase reverse transcriptase (hTERT) and c-myc were determined by real-time RT-PCR and Western blotting. Our results show that AL effectively inhibits proliferation in Hep-G2 cells in a concentrationand time-dependent manner. When Hep-G2 cells were treated with AL after 48h,the $IC_{50}$ was about 72.1 ${\mu}g/mL$. Apoptosis was induced by AL via arresting the cells in the G1 phase. Furthermore, AL effectively reduced telomerase activity through inhibition of mRNA and protein expression of hTERT and c-myc. Hence, these data demonstrate that AL exerts anti-proliferative effects in Hep-G2 cells via down-regulation of the c-myc/hTERT/telomerase pathway.

• Journal of Biosystems Engineering
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• v.7 no.2
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• pp.18-29
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• 1983

A low cost and versatile data acquisition system for the field and laboratory use was developed by using a single board microcomputer. Data acquisition system based on a Z80 microprocessor was built, tested and modified to obtain the present functional system. The microcomputer developed consists of 6 kB ROM, 5 kB RAM, 6-seven segment LED display, 16-Hex. key and 8 command key board. And it interfaces with an 8 channel, 12 bits A/D converter, a microprinter, EPROM programmer for 2716, and RS232C interface to transfer data between the system and HP3000 mini-computer manufactured by Hewlett Packard Co., A software package was also developed, tested, and modified for the system. This package included drivers for the AID converter, LED display, key board, microprinter, EPROM programmer, and RS232c interface. All of these programs were written in 280 assembler language and converted to machine codes using a cross assembler by HP3000 computer to the system during modifying stage by data transferring unit of this system, then the machine language wrote to the EPROM by this EPROM programmer. The results are summarized as follows: 1. Measuring program developed was able to control the measuring intervals, No. of channels used, and No. of data, where the maximum measuring speed was 58.8 microsec. 2. Calibration of the system was performed with triangle wave generated by a function generator. The results of calibration agreed well to the test results. 3. The measured data was able to be written into EPROM, then the EPROM data was compared with original data. It took only 75 sec. for the developed program to write the data of 2 kB the EPROM. 4. For the slow speed measurements, microprinter instead of EPROM programmer proved to be useful. It took about 15 min. for microprinter to write the data of 2 kB. 5. Modified data transferring unit was very effective in communicating between the system and HP3000 computer. The required time for data transferring was only 1~2 min. 6. By using DC/DC converting devices such as 78-series, 79-series. and TL497 IC, this system was modified to convert the only one input power sources to the various powers. The available power sources of the system was DC 7~25 V and 1.8 A.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.73-73
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• 2009

트렌지스터의 채널 길이가 줄어듦에 따라 절연층으로 쓰이는 $SiO_2$의 두께는 얇아져야 한다. 이에 따라 얇아진 절연층에서 터널링이 발생하여 누설전류가 증가하게 되어 소자의 오동작을 유발한다. 절연층에서의 터널링을 줄여주기 위해서는 High-K와 같은 유전율이 높은 물질을 이용하여 절연층의 두께를 높여주어야 한다. 최근에 각광 받고 있는 High-K의 대표적인 물질은 $HfO_2$, $ZrO_2$와 $Al_2O_3$등이 있다. $HfO_2$, $ZrO_2$와 $Al_2O_3$는 $SiO_2$보다 유전상 수는 높지만 밴드갭 에너지, 열역학적 안정성, 재결정 온도와 같은 특성 면에서 $SiO_2$를 완전히 대체하기는 어려운 실정이다. 최근 연구에 따르면 기존의 High-K물질에 금속을 첨가한 금속산화물의 경우 밴드갭 에너지, 열역학적 안정성, 재결정 온도의 특성이 향상되었다는 결과가 있다. 이 금속 산화물 중 $HfAlO_3$가 대표적이다. $HfAlO_3$는 유전상수 18.2, 밴드캡 에너지 6.5 eV, 재결정 온도 $900\;^{\circ}C$이고 열역학적 안전성이 개선되었다. 게이트 절연층으로 사용될 수 있는 $HfAlO_3$는 전극과 기판사이에 적층구조를 이루고 있어, 이방성 식각인 건식 식각에 대한 연구가 필요하다. 본 연구는 $BCl_3$/Ar 유도결합 플라즈마를 이용하여 $HfAlO_3$ 박막의 식각 특성을 알아보았다. RF Power 700 W, DC-bias -150 V, 공정압력 15 mTorr, 기판온도 $40\;^{\circ}C$를 기본 조건으로 하여, $BCl_3$/Ar 가스비율, RF Power, DC-bias 전압, 공정압력에 의한 식각율 조건과 마스크물질과의 선택비를 알아보았다. 플라즈마 분석은 Optical 이용하여 진행하였고, 식각 후 표면의 화학적 구조는 X-ray Photoelectron Spectroscoopy(XPS) 분석을 통하여 알아보았다.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.11B no.3
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• pp.112-118
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• 2001

In the near future, the voltage of power system for passenger vehicle will be changed to 42V from existing 14V./ Because of increasing power and voltage ratings used in the vehicle the motor drive system has high switching dv/dt and it generates electromagnetic interference (EMI) To solve these problems multi-level inverter system may be used The feature of multi-level inverter is the output voltage to be synthesized from several levels of voltage Because of this feature high switching dv/dt and EMI can be reduced in the multi-level inverter system But as the number of level is increased manufacturing cost is getting expensive and system size is getting large. Because of these disadvantages the application of multi-level inverter has been restricted only to high power drives. The method to reduce manufacturing cost and system size is to integrate circuit of multi-level inverter into a few chips But isolated power supply and signal isolation circuit using transformer or opto-coupler for drive circuit are obstacles to implement the integrated circuit (IC) In this paper a drive circuit of 4-level inverter suitable for integration to hybrid or one chip is proposed In the proposed drive circuit DC link voltage is used directly as the power source of each gate drive circuit NPN transistors and PNP transistors are used to isolate to transfer the control signals. So the proposed drive circuit needs no transformers and opto-couplers for electrical isolation of drive circuit and is constructed only using components to be implemented on a silicon wafer With th e proposed drive circuit 4- level inverter system will be possible to be implemented through integrated circuit technology Using the proposed drive circuit 4- level inverter system is constructed and the validity and characteristics of the proposed drive circuit are proved through the experiments.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.144-144
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• 1999

최근 국내 반도체 기술의 비약적인 발전으로 전자 기기 전반에 소형화, 고주파화, 고기능화 등이 진행되는데 반해, 반도체 소자등에 전원을 공급하거나 회로 전체를 운용하는 전기 신호를 변조.증폭시키는데 반해, 반도체 소자등에 전원을 공급하거나 회로 전체를 운용하는 전기신호를 변조.증폭시키는 인덕터, 트랜스 포머와 같은 수동 자기 소자는 아직도 3차원 벌크 형태로 사용되고 있다. 일본을 중심으로 각국에서는 자기 소자의 박막.소형화에 대한 다각도의 연구가 진행되었으나 국내서는 아직 미미한 실정이다. 따라서 고집적 전원 공급 장치나 지능 센서 등에 반도체와 자기 소자의 사용 주파수 대역과 크기가 통합된 반도체-자성체 IC(semiconductor-magnetic integrated circuit)의 필요성이 절실히 요구되고 있다. 현재 사용중인 벌크형 인덕터나, 트랜스 포머의 경우 10NHz이상의 고주파 대역에는 응용되지 못하고 있다. 이는 적용된 자성체가 페라이트(ferrite)로서 초투자율은 크지만 고주파대역에서의 공진 현상에 의해 저투자율을 나타내고, 포화 자속밀도가 낮기 때문이다. 이러한 페라이트 자성체의 대체품으로 주목받고 있는 것이 Fe, Co계 고비저항 자성마이다. 그러나 Co는 낮은 포화자속밀도를 나타내기 때문에 이러한 조건을 충족시키는 자성막으로 Fe계 미세 결정막을 사용하였다. 본 연구에서는 선택적 전기 도금법(selective electroplating method)과 LIGA like process를 이용하여 공시형 인덕터(air core inductor)의 라이브러리(library)를 구축한 뒤, 고주파 대역에서의 우수한 연자기 특성을 가지는 Ti/FeTaN막을 적용한 자기 박막 인덕터(magnetic thin film inductor)를 제작하여 비교.분석하였다. 제조된 인덕터의 특성 추정은 impedence analyzer를 이용하여 주파수에 따른 저항(resistance), 인덕턴스(inductance)를 측정, 계산한 성능지수(quality factor)로서 인덕터의 성능을 평가하였다. 제조된 박막 인덕터의 코일 형상은 5턴의 double rectangular spiral 구조였으며, 적용된 자성막의 유효 투자율9effective permeability)은 1500, 자성막, 절연막 그리고 코일의 두께는 각각 2$\mu\textrm{m}$, 1$\mu\textrm{m}$, 20$\mu\textrm{m}$이며 코일의 폭은 100$\mu\textrm{m}$, 코일간의 간격은 100$\mu\textrm{m}$였다. 제조된 박막 인덕터는 5MHz에서 1.0$\mu$H의 인덕턴스를 나타내었으며 dc current dervability는 100mA까지 유지되었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.10 s.89
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• pp.1011-1017
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• 2004

Ultra Wideband(UWB) technologies have been developed to exploit a new spectrum resource in substances and to realize ultra-high-speed communication, high precision geolocation, and other applications. The energy of UWB signal is extremely spread from near DC to a few GHz. This means that the interference between conventional narrowband systems and UWB systems is inevitable. However, the interference effects had not previously been studied from UWB wireless systems to conventional mobile wireless systems sharing the frequency bands such as Korean Cellular CDMA and WCDMA. This paper experimentally evaluates the interference from two kinds of UWB sources, namely a direct-sequence spread-spectrum CDMA(DS-CDMA) UWB source and an impulse radio UWB source, to a Cellular CDMA and WCDMA digital transmission system. The average frame error rate degradation of each system are presented. From these experimental results, the interference effects of DS-CDMA UWB source is not severe compared to the Impulse UWB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.