• ETRI Journal
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• v.30 no.2
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• pp.344-346
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• 2008

In this paper, we present a novel oscillator (OSC) design. Bandpass filters, which can suppress harmonics, are incorporated into a co-design with an OSC to improve the OSC phase noise and harmonic rejection. The proposed OSC/bandpass filter co-design achieves a phase noise of -130.1 dBc/Hz/600 kHz and harmonic rejection of 37.94 dB and 40.85 dB for the second and third harmonics, respectively, as compared to results achieved by the OSC before co-design of -101.6 dBc/Hz/600 kHz and 21.28 dB and 19.68 dB. Good agreement between the measured and simulated results is achieved.

• Journal of the Optical Society of Korea
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• v.11 no.3
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• pp.108-112
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• 2007

Spectroscopic ellipsometry (SE) has become an important tool in scatterometry based nano-structure 3D profiling. In this paper, we propose a novel 3D nano object recognition method by use of phase sensitive scatterometry. We claims that only phase sensitive scatterometry can provide a reasonable 3D nano-object recognition capability since phase data gives much higher sensitive 3D information than amplitude data. To show the validity of this approach, first we generate various $0^{th}$ order SE spectrum data ($\psi$ and ${\Delta}$) which can be calculated through rigorous coupled-wave analysis (RCWA) algorithm and then we calculate correlation values between a reference spectrum and an object spectrum which is varied for several different object 3D shape.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• ETRI Journal
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• v.42 no.6
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.1
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• pp.45-52
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• 2021

The space vector control based voltage control method for a three-phase PWM rectifier requires a lot of effort to design an optimal switching pattern since a switching pattern for the switching section must be designed. In this study, a D-Q control based SPWM output voltage control algorithm was studied for the three-phase six-pulse CVS type rectifier. In the output voltage control algorithm, three-phase reference signals are obtained from the D-Q transformation based on the space vector representation method, instead of the switching pattern, SPWM method is used to generate rectifier switching control signals. Next, a three-phase six-pulse CVS PWM rectifier based on D-Q transformation and SPWM was modeled using EMTP-RV. Finally, the validity of the D-Q control-based SPWM voltage control algorithm was confirmed by comparing the output voltage waveform obtained through EMTP-RV simulation works with a reference value and confirming that the output voltage accurately follows the reference voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.629-633
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• 2015

An active balun using current steering for phase correction is presented. The proposed active balun is constructed with two different unit balun structures based on current steering to reduce phase and amplitude errors. This type of topology can be compared with the conventional phase and amplitude correction techniques which do not incorporate the current steering. Designed and fabricated active balun in $0.18{\mu}m$ CMOS process operates over 0.95 - 1.45 GHz band, showing input reflection coefficient under -15 dB, phase error of $11^{\circ}$ and gain error of 0.5 dB. Gain is measured to be 0.3 dB maximum and power consumption of 7.2 mW is measured.

• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.5
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• pp.629-636
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• 2014

In the proposed paper, we designed low phase noise frequency synthesizer for Ku-band. The proposed up-mixing frequency synthesizer consists of narrow local oscillation part and variable frequency oscillation part. To improve the phase noise of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise. The implemented frequency synthesizer reduce the phase noise. The phase noise is -95.18dBc/Hz at 7kHz frequency offset in 16GHz and -94.27dBc/Hz at 7kHz frequency offset in 16.125GHz.

• International conference on construction engineering and project management
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• 2022.06a
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• pp.768-775
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• 2022

Current MEP designs are mostly applied by 2D-based design methods and tend to focus on simple modeling or geometry information expression such as converting 2D-written drawings into 3D modeling without taking advantage of the strength of BIM application. To increase the demand for BIM-based MEP design, geometric information, and property information of each member of the 3D model must be conveniently linked from the phase of the Design Development (DD) to the phase of Construction Document (CD). To conveniently implement a detailed model at each phase, the detailed level of each member of the 3D model must be specific, and an automatic generation of objects at each phase and automatic detailing module for each LOD are required. However, South Korea's guidelines have comprehensive standards for the degree of MEP modeling details for each design phase, and the application of each design phase is ambiguous. Furthermore, in practice, detailed levels of each phase are input manually. Therefore, this paper summarized the detailed standards of MEP modeling for each design phase through interviews with MEP design companies and related literature research. In addition, items that enable auto-detailing with DYNAMO were selected using the checklist for each design phase, and the types of detailed methods were presented. Auto-detailing items considering the detailed level of each phase were classified by members. If a DYNAMO algorithm is produced that automates selected auto-detailing items in this paper, the time and costs required for modeling construction will be reduced, and the demand for MEP design will increase.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.151-158
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• 2002

In this paper, Phase locked microwave oscillator having the low phase noise and high stability for digital MMDS down converter was designed. we have been analyzed the low phase noise properties by the active device nonlinear equivalent circuits and derived the necessary and sufficient conditions for high stable voltage control oscillator. And it is applied to phase locked loop, we design the phase locked microwave oscillator of frequency synthesizer. Experimental results of designed phase locked oscillator shows -85dBc/Hz @ 10KHz phase noise properties and simulation result is -90Bc/Hz @ 10kHz respectively we shows that proposed low phase noise and stable conditions of phase locked microwave oscillator can be applied to design the high stable digital MMDS frequency synthesizer.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.546-547
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• 2012

In the three-phase power system using the three-phase load, when any one-phase is open-phase, the unbalanced current flows and the single-phase power supplied by power supply produces over-current. As a result, the enormous damage and electrical fire can be given to the power system. In order to improve these problems, this paper is proposed a new control circuit topology for open-phase protection using semiconductor devices. Therefore, the proposed open-phase protection device (OPPD) enhances the sensing speed and precision, and has the advantage of simple fitting in the three-phase distribution panel in the field, as it manufactures into small size and light weight. As a result, the proposed OPPD minimizes the electrical fire from open-phase, and contributes for the stable driving of the power system.