• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.227-236
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• 2017

Quantum-dot cellular automata(QCA) consists of nano-scale cells and demands very low power consumption so that it is one of the alternative technologies that can overcome the limits of scaling CMOS technologies. Various circuits on QCA have been researched until these days, a latch required for counter and state control has been proposed as a component of sequential logic circuits. A latch uses a feedback loop to maintain previous state. In QCA, a latch uses a square structure using 4 clocks for feedback loop. Previous latches have been proposed using many cells and clocks in coplanar. In this paper, in order to eliminate these defects, we propose a SR and D latch using multilayer structure on QCA. Proposed three dimensional loop structure is based on multilayer and consists of 3 layers. Each layer has 2 clock differences between layers in order to reduce interference. The proposed latches are analyzed and compared to previous designs.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.54-61
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• 1998

A new Triple well structure is proposed for improved latch-up immunity at deep submicron CMOS device. Optimum latch-up immunity process condition is established and analyzed with varying ion implantation energy and amount of dose and also compared conventional twin well structure. Doping profile and structure are investigated using ATHENA which is process simulator, and then latch-up current is calculated using ATLAS which is device simulator. Two types of different process are affected by latch-up characteristics and shape of doping profiles. Finally, we obtained the best latch-up immunity with 2.5[mA/${\mu}{m}$] trigger current using 2.5 MeV implantation energy and 1$\times$10$^{14}$ [cm$^{-2}$ ] dose at p-well

• The Journal of the Convergence on Culture Technology
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• v.6 no.2
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• pp.515-520
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• 2020

CMOS used in digital circuit design technology has reached the limit of integration due to quantum tunneling. Quantum-dot cellular automata (QCA), which can replace this, has many advantages such as low power consumption and fast switching speed, so many digital circuits of CMOS have been proposed based on QCA. Among them, the multiplexer is a basic circuit used in various circuits such as D-flip-flops and resistors, and has been studied a lot. However, the existing multiplexer has a disadvantage that space efficiency is not good. Therefore, in this paper, we propose a new multilayered multiplexer using cell interaction and D-latch using it. The multiplexer and D-latch proposed in this paper have improved area, cell count, and delay time, and have excellent connectivity and scalability when designing large circuits. All proposed structures are simulated using QCADesigner to verify operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.41-46
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• 2017

In this study, rapid cooling method was proposed to improve the anti-scratch performance of anti-reflection film fabricated by nanoimprint lithography. Effects of cooling time on the mechanical properties and optical properties were evaluated. Pencil hardness measurements showed that anti-scratch performance enhanced as the cooling time increased while characterization on the optical property showed that reflectance on scratch increased as the cooling time increased. Therefore, it was concluded that the anti-scratch performance and optical properties are highly influenced by the cooling time. The observed results explained in terms of residual stress and free volume in polymeric materials.

• The KIPS Transactions:PartD
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• v.11D no.4
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• pp.809-822
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• 2004

In this paper, we propose a concurrency control algorithm based on R-tree for spatial database management system. The previous proposed algorithms can't prevent problem that search operation is to be blocking during update operations. In case of multidimensional indexes like R-tree, locking of update operations may be locked to several nodes, and splitting of nodes have to lock a splitting node for a long time. Therefore search operations have to waiting a long time until update operations unlock. In this paper we propose new algorithms for lock-free search operation. First, we develop a new technique using a linked-list technique on the node. The linked-list enable lock-free search when search operations search a node. Next, we propose a new technique using a version technique. The version technique enable lock-free search on the node that update operations is to be splitting.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.295-300
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• 2005

In this paper we have designed a two-stage Class I power amplifier operated at 2.4CHz for Class-1 Bluetooth application. The power amplifier employs class-I topology to exploit its soft-switching property for high efficiency. The latch-structured pre-amplifier with amplifiers makes its output signal as sharp as possible for soft switching of the next power amplifier. It improves the overall efficiency of the proposed power amplifier. It shows 65.8$\%$ PAE, 20dB power gain and 20dBm output power.

• Journal of IKEEE
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• v.25 no.2
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• pp.376-380
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• 2021

In this paper, we propose a novel ESD protection device with Latch-up immunity properties due to high holding voltages by improving the structure of a typical SCR. To verify the characteristics of the proposed ESD circuit, simulations were conducted using Synopsys TCAD and presented compared to existing ESD protection circuits. Furthermore, the variation of electrical properties was verified using the design variable D1. Simulation results confirm that the proposed ESD protective circuit has higher holding voltage properties and bidirectional discharge properties compared to conventional ESD protective circuits. We validate the electrical properties with post-design TLP measurements using Samsung's 0.13um BCD process. And we verify that the proposed ESD protection circuit in this paper is well suited for high voltage applications in that it has a latch-up immunity due to improved holding voltage through optimization of design variables.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2014.04a
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• pp.269-270
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• 2014

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.48-54
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• 1999

We designed the optimal device parameters of the retrograde well and the gettering layer(buried layer) using the high energy ion implantation for the next generation of CMOS struoture and proposed two models and simulated these models with Athena and Atlas, Silvaco Co. We obtained trigger currents which is more than 600 ${\mu}A/{\mu}m$ when the structure has been combined the gettering layer and the retrograde well. And the second model(twin retrograde well) was obtained that holdingcurrents were over 2500${\mu}A/{\mu}m$. As results, the more heavier dose, the more improved the latch-up immunity. The n'-p' spacing was fixed a 2${\mu}m$ in both models.