• Journal of Power Electronics
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• v.7 no.3
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• pp.222-232
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• 2007

This paper presents the application of a single phase AC-to-DC converter using a three-phase series parallel (SPRC) resonant converter to variable speed dc-drive. The improved power quality converter gives the input power factor unity over a wide speed range, reduces the total harmonic distortion (THD) of ac input supply current, and makes very low ripples in the armature current and voltage waveform. This soft-switching converter not only possesses the advantages of achieving high switching frequencies with practically zero switching losses but also provides full ranges of voltage conversion and load variation. The proposed drive system is the most appropriate solution to preserve the present separately excited de motors in industry compared with the use of variable frequency ac drive technology. The simulation and experimental results are presented for variable load torque conditions. The variable frequency control scheme is implemented using a DSP- TMS320LF2402. This control reduces the switching losses and current ripples, eliminates the EMI and improves the efficiency of the drive system. Experimental results confirm the consistency of the proposed approach.

• Journal of Power Electronics
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• v.5 no.4
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• pp.247-256
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• 2005

In order to harvest power in an efficient manner from a micro piezoelectric (PZT) device for charging the battery of a remote system, a new AC/DC resonant pulse power converter is proposed. The proposed power converter has two stages in the power conversion process. The first stage includes N-type MOSFET full bridge rectifier. The second stage includes a boost converter having an N-type MOSFET and a P-type MOSFET. MOSFETs work in the $1^{st}$ or $3^{rd}$ quadrant region. A small inductor for the boost converter is assigned in order to make the size of the power converter as small as possible, which makes the on-interval of the MOSFET switch of the boost converter ultimately short. Due to this short on-interval, the parasitic junction capacitances of MOSFETs affect the performance of the power converter system. In this paper, the performance of the new converter is analytically and experimentally evaluated with consideration of the parasitic capacitance of switching devices.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.91-97
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• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.394-395
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• 2011

In order to increase the power conversion efficiency and improve the power factor, a modified forward converter is proposed, which adopts a capacitive output filter instead of the inductive output filter of the conventional forward converter. Therefore, the proposed converter has wide input voltage range in opposite to that of the conventional forward converters. Moreover, the proposed converter uses the critical conduction mode for automatic current shaping to improve the power factor. As a result, the proposed converter can achieve quasi-resonant zero-voltage-switching, which can minimize the switching loss of main MOSFET. In addition, the operational principle of the proposed converter is analyzed and the characteristic of the proposed converter is investigated in this paper. To validate the effectiveness of the proposed converter, a prototype of 13W is implemented and the experimental results are discussed in more detail.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.13-19
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• 1999

This paper describes a design of an 8-bit 100KSPS 1mW CMOS A/D Converter. Using a novel systematic offset cancellation technique, we reduce the systematic offset voltage of operational amplifiers. Further, a new Gain amplifier is proposed. The proposed A/D Converter is fabricated with a $0.6{\mu}m$ single-poly triple-metal n-well CMOS technology. INL and DNL is within ${\pm}1LSB$, and SNR is about 43dB at the sampling frequency of 100KHz. The power consumption is $980{\mu}W$ at +3V power supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.2
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• pp.840-845
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• 2013

In this paper, the broadband frequency double down-converter based on LC filter technologies has been designed and implemented, and its performances are introduced. The Designed frequency double down-converter is consisted with a low-noise amplifier, mixer, IF amplifier, LC filter, DC-block capacitor and RF-bypass capacitor. Especially, instead of active devices of a typical converter, the suggested converter designed using passive devices to provide both low-power consumption and low-cost model. As results of the measurement, the implemented frequency double down-converter realizes the broadband performance with the bandwidth of 100MHz (13~113MHz) at the center frequency of 63MHz, and its gain is approximately 40dB.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.1944-1953
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• 2014

This paper shows the design and control methods of the bidirectional DC-DC converter to generate the proper DC-link voltage of a PMSM drive. Conventionally, because the controllable power of the PWM based voltage source inverter is limited by its DC-link voltage, the DC-DC converter is used for boosted DC-link voltage if the inverter source cannot generate enough operating voltage for the PMSM drive. In this paper, to obtain more utilization of this DC-DC converter, optimal DC-link voltage control for PMSM drive will be explained. First, the process and current path of the DC-DC converter will be illustrated, and a control method of this converter for variable DC-link voltage will then be explained. Finally, an improvement analysis of the optimal DC-link voltage control method, especially on the deadtime effect, will be explained. The DC-DC converter of the proposed control method is verified by the experiments by comparing with the conventional constant voltage control method.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1679-1685
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• 1989

In this paper, a new design of GaAs level converter is proposed, and anlyzed wth the variation of the threshold voltage of E/D MESFETs. The threshold voltage ranges analyzed are -0.05V to 0.35V for enhancement type MESFETs and -0.3V to -0.7V for depletion type MESFETs. In this range, the variation of the input characteristics of the conventional level converter designed to convert the level of DCFL using Vss of -0.8V to that of -0.2V, is greather than 600mV, but of the level converter proposed here is less than 100mV.