• Journal of Korean Port Research
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• v.8 no.2
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• pp.1-35
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• 1994

The main arterial which runs through the in City of Pusan, carries about 60% of downtown traffic or more, maintains about 20% yearly increase in traffic is severely suffering from the traffic congestion because of concentrated traffic volumes regardless of peak-time periods. The purpose of this study was to grasp the traffic, geometric, and signal conditions of the main arterial through the Videologging System Techniques, perform the transportation system analyses, and finally suggest the improvements which could increase the travel capacity, reduce the average delay and fuel consumption with the optimal conditions of signal system. The following conclusions were drawn : firstly the traffic system should be shifted for the travel distribution on the arterial during the peak time periods, secondly the roadway system of the arterial reviewed for left-turn traffic during the peak time periods, and thirdly the signal system of intersection reconstructed for signal optimization or progression within the range of cycle length suggested.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.31-38
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• 1998

This paper deals with CBS(Cycle Base Simulator) design of a 32 bit floating point DSP(Digital Signal Processor). The CBS has been developed for TMS320C30 compatible DSP and will be used to confirm the architecture, functions of sub-blocks, and control signals of the chip before the detailed logic design starts with VHDL. The outputs from CBS are used as important references at gate level design step because they give us control signals, output values of important blocks, values from internal buses and registers at each pipeline step, which are not available from the commercial simulator of DSP. In addition to core functions, it has various interfaces for efficient execution and convenient result display, CBS is verified through comparison with results from the commercial simulator for many application algorithms and its simulation speed is as fast as several tenth of that of logic simulation with VHDL. CBS in this work is for a specific DSP, but the concept may be applicable to other VLSI design.

• Journal of the Korea Society for Simulation
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• v.16 no.4
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• pp.13-22
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• 2007

Fault detection of cycle-based signals is typically performed using statistical approaches. Univariate SPC using few representative statistics and multivariate analysis methods such as PCA and PLS are the most popular methods for analyzing cycle-based signals. However, such approaches are limited when dealing with information-rich cycle-based signals. In this paper, process fault defection method based on wavelet analysis is proposed. Using Haar wavelet, coefficients that well reflect the process condition are selected. Next, Hotelling's $T^2$ chart using selected coefficients is constructed for assessment of process condition. To enhance the overall efficiency of fault detection, the following two steps are suggested, i.e. denoising method based on wavelet transform and coefficient selection methods using variance difference. For performance evaluation, various types of abnormal process conditions are simulated and the proposed algorithm is compared with other methodologies.

• Journal of Korean Society of Transportation
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• v.27 no.5
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• pp.179-187
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• 2009

This study develops a real-time signal control algorithm based on sectional travel times and includes a field test and evaluation. The objective function of the signal control algorithm is the equalization of delay of traffic movements, and the main process is calculating dissolved time of the queue and delay using the sectional travel time and detection time of individual vehicles. Then this algorithm calculates the delay variation and a targeted red time and calculates the length of the cycle and phase. A progression factor from the US HCM was applied as a method to consider the effect of coordinating the delay calculation, and this algorithm uses the average delay and detection time of probe vehicles, which were collected during the accumulated cycle for a stabile signal control. As a result of the field test and evaluation through the application of the traffic signal control algorithm on four consecutive intersections at 400m intervals, reduction of delay and an equalization effect of delay against TOD control were confirmed using the standard deviation of delay by traffic movements. This study was conducted to develop a real-time traffic signal control algorithm based on sectional travel time, using general-purpose traffic information detectors. With the current practice of disseminating ubiquitous technology, the aim of this study was a fundamental change of the traffic signal control method.

• Journal of Korean Society of Transportation
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• v.10 no.3
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• pp.7-20
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• 1992

The common cycle time for the linded signals is usually determined for the critical intersecion, just because the cpacity of a signalized intersection depends on the cycle time. This may not be optimal since the interactions between the flow and the spatial structure of the route or the area are disregarded in this case. It is common to separate the total delay incurred at signals into two parts, a deterministic or uniform delay and a stochastic or random delay. The deterministic delays and the stochastic delays on the artery particularly related to signal cycle time. For this purpose a microscopic simulation technique is used to evaluate deterministic delays, and a macroscopic simulation technique based on the principles of Markov chains is used to evaluate stochastic delays with over flow queue. As a result of investigating the relations between deterministic delays and cycle time in the various circumstances of spacing of signals and traffic volume. As for stochastic delays the resalts of comparisons of the macroscopic simulation and Newell's approximation with the microscopic simulation indicate that the former is valid for the degree of saturation less than 0.95 and the latter is for that above 0.95. Newell's argument that the total stochastic delay on an arterial is dominated by that at or caused by critical intersection is certified by the simulation experiments. The comprehensive analyses of the values of optimal cycle time with various conditions lead to a model. The cycle time determined by this model shows to be approximately 70% of that calculated by Webster's.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1858-1862
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• 2005

Stepping motor normally operates without feedback and may loss the synchronization. This problem can be prevented by using positional feedback. This paper introduces one method for closed loop control of stepping motor and a method for combining full-step control and micro-step control. This combination controlling apparatus can perform position control with high accuracy in a high speed, so that it will not suffer from vibration (or hunting) problem when stopping motor. Controlling apparatus contains a position counter block for detecting rotor position of stepping motor, a driving block for supplying current to windings of stepping motor, a control block for comparing output signal of position counter block with command position (desired position) and outputting current command signal based on deviation between current position and command position of rotor. To output current command signal, the control block refers to a sine wave data table. This table contains value of duty cycle of Pulse Width Modulation signal. As the second object of this paper, the process of building this data table is also presented.

• Journal of the Korean Society for Nondestructive Testing
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• v.33 no.2
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• pp.198-204
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• 2013

Acoustic emission(AE) signal was detected during charge and discharge of lithium ion battery to investigate relationships among cumulative count, discharge capacity, and microdamages. AE signal was received during accelerated charge/discharge cycle test of a coin-type commercial battery. A number of AE signals were successfully detected during charge and discharge, respectively. With increasing number of cycle, discharge capacity was decreased and AE cumulative count was observed to increase. Microstructural observation of the decomposed battery after cycle test revealed mechanical damages such as interface delamination and microcracking of the electrodes. These damages were attributed to sources of the detected AE signals. Based on a linear correlation between discharge capacity and cumulative count, feasibility of AE technique for evaluation of battery degradation was suggested.

• BMB Reports
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• v.29 no.4
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• pp.359-364
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• 1996

By both in vitro hydroxylamine mutagenesis of the wild type 3-phosphoglycerate kinase gene (PGK) promoter DNA and insertion of the leu2-d gene, we have created yeast expression vectors potentially useful for production of eukaryotic genes in yeast. The guanine (G) to adenine (A) change at the -3 position from the ATG start codon of the PGK promoter-based vector rendered a 6~7 times elevated expression of the adjacent eukaryotic gene, and insertion of the leu2-d gene in the vector containing the mutated PGK promoter further enhanced the expression of the gene. When expression of the AIDS virus HIV1-gagP17 gene in a lacZ fusion form was examined with this new vector, a 15 times higher level of expression than that from the original PGK promoter was observed. Northern and Southern analysis showed that this elevated expression is due to the production of a high copy number of mRNA by leu2-d gene functioning and by efficient translation of the produced mRNA. Thus, the vector that contained the A at the -3 position from the ATG start codon in the promoter region and the leu2-d gene shows increased expression capability and will be potentially useful for production of eukaryotic genes in yeast.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.22 no.6
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• pp.182-195
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• 2023

Recently, research on traffic signal control using artificial intelligence algorithms has been receiving attention, and many traffic signal control models are being studied. However, most studies either focused on independent intersections or are theoretical studies that calculate signal cycle length according to changes in traffic volume. Therefore, this study was conducted on a signalized intersection - roundabout in Gajwa-ro. The Particle Swarm Optimization - Bacterial Foraging Optimization (PSO-BFO) algorithm was proposed, which is developed from the GA and PSO algorithms for minimizing congestion at two intersections. As a result, optimum cycle length was determined to be 158 seconds. The Verkehr In Stadten - SIMulationsmodell (VISSIM) results showed that there was 3.4% increased capacity, 8.2% reduced delay and 8.3% reduced number of stops at the Gajwa-ro signalized intersection. Additionally, at the roundabout, a 9.2% increase in capacity, a 7.1% reduction in delay, and a 27.2% decrease in the number of stops was observed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.