• Asian Journal of Atmospheric Environment
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• 제10권1호
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• pp.13-21
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• 2016

The vertical distributions of aerosol extinction coefficient were estimated using the scaling height retrieved at Gwangju, Korea ($35.23^{\circ}N$, $126.84^{\circ}E$) during a spring season (March to May) of 2009. The aerosol scaling heights were calculated on a basis of the aerosol optical depth (AOD) and the surface visibilities. During the observation period, the scaling heights varied between 3.55 km and 0.39 km. The retrieved vertical profiles of extinction coefficient from these scaling heights were compared with extinction profile derived from the Light Detection and Ranging (LIDAR) observation. The retrieve vertical profiles of aerosol extinction coefficient were categorized into three classes according to the values of AODs and the surface visibilities: (Case I) the AODs and the surface visibilities are measured as both high, (Case II) the AODs and the surface visibilities are both lower, and (Others) the others. The averaged scaling heights for the three cases were $3.09{\pm}0.46km$, $0.82{\pm}0.27km$, and $1.46{\pm}0.57km$, respectively. For Case I, differences between the vertical profile retrieved from the scaling height and the LIDAR observation was highest. Because aerosols in Case I are considered as dust-dominant, uplifted dust above planetary boundary layer (PBL) was influenced this discrepancy. However, for the Case II and other cases, the modelled vertical aerosol extinction profiles from the scaling heights are in good agreement with the results from the LIDAR observation. Although limitation in the current modelling of vertical structure of aerosols exists for aerosol layers above PBL, the results are promising to assess aerosol profile without high-cost instruments.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권2호
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• pp.103-110
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• 2001

Gate oxide scaling for sub-l00nm CMOS devices has been studied. Issues on the gate oxide scaling are reviewed, which are boron penetration, reliability, and direct tunneling leakage currents. Reliability of Sub-2.0nm oxides and the device performance degradation due to boron penetration are investigated. Especially, the effect of gate leakage currents on the transistor characteristics is studied. As a result, it is proposed that thinner oxides than previous expectations may be usable as scaling proceeds. Based on the gate oxide thickness optimization process we have established, high performance CMOS transistors of $L_{gate}=70nm$ and $T_{ox}=1.4nm$ were fabricated, which showed excellent current drives of $860\mu\textrm{A}/\mu\textrm{m}$ (NMOS) and $350\mu\textrm{A}/\mu\textrm{m}$ (PMOS) at $I_{off}=10\mu\textrm{A}/\mu\textrm{m}$ and $V_dd=1.2V$, and CV/I of 1.60ps (NMOS) and 3.32ps(PMOS).

• Progress in Superconductivity
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• 제9권2호
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• pp.152-156
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• 2008

Detailed field and strain dependence of the critical current and the n-value for an internal-tin processed $Nb_3Sn$ strand have been measured. Both the compressive and tensile strain is applied reversibly using Walter spiral probe made of BeCu up to 0.73 %. There is a correlation between the critical current and the n-value for the $Nb_3Sn$ strand studied in this work and the field dependence of the n-value is in agreement with a recent empirical formula. It was further shown that the critical current can be reasonably well fitted by the scaling law based on strong-coupling theory of superconductivity using the relation between the critical current and the n-value.

• Transactions on Electrical and Electronic Materials
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• 제11권3호
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• pp.93-105
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• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 춘계학술대회 논문집
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• pp.109-113
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• 1996

In this work, a scaling methodology to scale down to or below 0.1$\mu\textrm{m}$ is presented, considering a current process technology. 0.12$\mu\textrm{m}$ nMOSFET's with both good performance and reliability is designed by this methodology

• 농업과학연구
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• 제49권3호
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• pp.431-440
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• 2022

Hanwoo cattle are a unique and historical breed in Korea that have been genetically improved and maintained by the national evaluation and selection system. The aim of this study was to provide information that can help improve the accuracy of the estimated breeding values in Hanwoo cattle by showing the difference between the imputation reference chip platforms of genomic data and the scaling factor of the genetic relationship matrix (GRM). In this study, nine sets of data were compared that consisted of 3 reference platforms each with 3 different scaling factors (-0.5, 0 and 0.5). The evaluation was performed using MTG2.0 with nine different GRMs for the same number of genotyped animals, pedigree, and phenotype data. A five multi-trait model was used for the evaluation in this study which is the same model used in the national evaluation system. Our results show that the Hanwoo custom v1 platform is the best option for all traits, providing a mean accuracy improvement by 0.1 - 0.3%. In the case of the scaling factor, regardless of the imputation chip platform, a setting of -1 resulted in a better accuracy increased by 0.5 to 1.6% compared to the other scaling factors. In conclusion, this study revealed that Hanwoo custom v1 used as the imputation reference chip platform and a scaling factor of -0.5 can improve the accuracy of the estimated breeding value in the Hanwoo population. This information could help to improve the current evaluation system.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2008년도 High Temperature Superconductivity Vol.XVIII
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• pp.62-62
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• 2008

• Journal of Welding and Joining
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• 제28권5호
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• pp.99-105
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• 2010

Inverter DC resistance spot welding process has been very widely used for joining such as automotive body sheet metal. Because the lobe area of DC welding is larger than AC welding and DC welding has low electrode wear. So the use of Inverter DC resistance spot welding process has been further increased. And the application of high tensile steel is growing for light weight vehicle. To improve the weldability of high strength steel, the development of Inverter DC resistance spot welding system is more conducted. However, Inverter DC resistance spot welding system has a few problems. Current waveform is unstable and the expulsion has been occurred by characteristics of steel. In this study, inverter DC resistance spot welding system was made. And Fuzzy control algorithm was applied for constant current. The genetic algorithm was applied to optimize the fuzzy scaling factors, in order to optimize the fuzzy control.

• 응용통계연구
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• 제27권4호
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• pp.619-627
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• 2014

다차원척도법(MDS)에서는 대게 개체간의 거리나 유사성이 대칭성을 따른다. 따라서 비대칭 거리를 다루기는 쉽지 않다. 통용되고 있는 비대칭 다차원척도법도 여전히 결과를 해석하는데 어려움이 있다. 본 연구는 비대칭행렬의 순서 통계량을 활용하여 더 간단한 비대칭 대차원척도법을 제안한다. 제안된 웹(Web) 방법은 개체간의 영향력을 사용자들이 해석을 쉽게 하도록 화살표의 방향크기와 모양에 따라 시각화하여 보여준다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 심포지엄 논문집 정보 및 제어부문
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• pp.279-281
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• 2006

In this paper, we study an approach to design a self-tuning Fuzzy-PI controller in HVDC(High Voltage Direct Current) system. In the rectifier of conversional HVDC system, turning on, turning off, triggering and protections of thyristors have lots of problems that can make the dynamic instability and cannot damp the dynamic disturbance efficiently. The above problems are solved by adapting Fuzzy-PI controller for the fire angle control of rectifier.[7] The performance of the Fuzzy-PI controller is sensitive to the variety of scaling factors. The design procedure dwells on the use of evolutionary computing(Genetic Algorithms, GAs). Then we can obtain the optimal scaling factors of the Fuzzy-PI controller by Genetic Algorithms. In order to improve Fuzzy-PI controller, we adopt FIS to tune the scaling factors of the Fuzzy-PI controller on line. A comparative study has been performed between Fuzzy-PI and self-tuning Fuzzy-PI controller, to prove the superiority of the proposed scheme.