• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.1
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• pp.40-47
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• 2003

A low-cost current-sensing scheme for the motor drives with MOSFET is described. Many motor drives usually employ the common current sensors to measure current for the purpose of control or protection. These current sensors, however, significantly burden the power circuit with the size and cost. The proposed current-sensing scheme utilizes information concerning MOSFET's On-voltage and On-resistance. An analogue circuit detecting On-voltage can overcome the above disadvantages because the circuit is small and is made at a low cost, and the fuzzy inference for On-resistance is also simply designed based on MOSFET's characteristics. The validity of this scheme will be experimentally verified by adopting the current control of a battery car.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.86-90
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• 2007

An efficient sensing scheme applicable to DC-DC converters is proposed. The output voltage of the DC-DC converter is fed back and converted to a current signal at the input terminal of the sensor to decide if it is in the tolerable range. The comparison is accomplished by a current push-pull action. With the embedded reference current in the sensor realized from the reference voltage. The advantages of the scheme lie in the fairly accurate and efficient implementation in terms of power consumption and chip size overhead compared with conventional voltage-mode schemes as the major parameter in converting voltage to current is determined by (W/L) aspect ratio of the core transistors. In this paper, a DC-DC converter of 5V output from battery range of 2.2V${\sim}$3.6V adopting the proposed sensing scheme is implemented in a 0.35um CMOS process to prove the validity of the scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.363-369
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• 2017

Phase-change random access memory (PRAM) has been emerged as a potential memory due to its excellent scalability, non-volatility, and random accessibility. But, as the cell current is reducing due to cell size scaling, the read-sensing window margin is also decreasing due to increased variation of cell performance distribution, resulting in a substantial loss of yield. To cope with this problem, a novel adaptive read-sensing reference current generation scheme is proposed, whose trimming range and resolution are adaptively controlled depending on process conditions. Performance evaluation in a 58-nm CMOS process indicated that the proposed read-sensing reference current scheme allowed the integral nonlinearity (INL) to be improved from 10.3 LSB to 2.14 LSB (79% reduction), and the differential nonlinearity (DNL) from 2.29 LSB to 0.94 LSB (59% reduction).

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.982-986
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• 1998

The peak-power-tracking solar array regulator sensing the inductor current is proposed. Since it uses the inductor current as the solar array output power information, the PPT control scheme can be greatly simplified. The charge controlled two-loop scheme is presented to improve the dynamics due to the inductor current sensing. The comparison between the single-voltage loop controlled system and the two-loop controlled system employing the charge control is presented. This paper also contains the simulation results of that comparison.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.1-11
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• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.529-530
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• 2006

An efficient sensing scheme adoptable in DC-DC converter is described. The output voltage of the whole DC-DC converter is fed back to the input voltage of the sensor. The comparison in the sensor is accomplished by a current push-pull action. With a fixed reference, the comparator can be embodied based on (W/L) ratios. The current-mode scheme benefits the system better than a conventional voltage-mode one in terms of small area, low power consumption.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.195-196
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• 2012

In recent years, in an effort to improve the efficiency and the power density of the front-end power factor correction(PFC), the interleaving of multiple converter is employed. The conventional interleaved continuous conduction mode(CCM) boost PFC converter requires input and output voltage sensing and three current sensing to obtain current balancing between modules. In this paper, the interleaved CCM PFC converter based on modulated carrier control is proposed. With the proposed method, two phase interleaved PFC can be realized simply without line voltage sensing resistor and can achieve current balancing without additional current sensing resistor on common return path. The simulation studies are carried out to verify the effectiveness of the proposed control scheme.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.419-422
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• 2004

A sensing scheme for current-mode magneto-resistance random access memory (MRAM) with a 1T1MTJ cell structure is proposed. Magnetic tunnel junction (MTJ) resistance, which is HIGH or LOW, is converted to different cell currents during READ operation. The cell current is then amplified to be evaluated by the reference cell current. In this scheme, conventional bit line sense amplifiers are not required and the operation is less sensitive to voltage noise than that of voltage-mode circuit is. It has been confirmed with HSPICE simulations using a 0.35-${\mu}m$ 2-poly 4-metal CMOS technology.

• Current Optics and Photonics
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• v.2 no.4
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• pp.315-323
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• 2018

A new multiple-image encryption scheme that is based on a compressive ghost imaging concept along with a Fourier transform sampling principle has been proposed. This further improves the security of the scheme. The scheme adopts a Fourier transform to sample the original multiple-image information respectively, utilizing the centrosymmetric conjugation property of the spatial spectrum of the images to obtain each Fourier coefficient in the most abundant spatial frequency band. Based on this sampling principle, the multiple images to be encrypted are grouped into a combined image, and then the compressive ghost imaging algorithm is used to improve the security, which reduces the amount of information transmission and improves the information transmission rate. Due to the presence of the compressive sensing algorithm, the scheme improves the accuracy of image reconstruction.