• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.512-512
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• 2000

In this article, a current mode peak detector circuit is presented. The simple circuit configuration comprises four MOS transistors and one external capacitor. The realization method is suitable fur fabrication using CMOS technology and all transistors are operated in their saturation region. The proposed circuit exhibits a very low drop rate and provides high accuracy, high-speed and wide dynamic range. The proposed circuit has very low power dissipation and operates using a single 2.5V supply. Simulation results confirmed the characteristic of the proposed circuit are also included.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• Journal of Power Electronics
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• v.12 no.2
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• pp.242-248
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• 2012

Self oscillating current fed push pull resonant inverters can be controlled without using special drivers. Dc current flows through the choke coil and the power switches, although the driving signals of the power switches are sinusoidal. When the base current is near zero, the transistors cannot be operated in switching mode. Hence higher switching power losses and instantaneous peak power during off transitions are observed. In this study, an alternative design has been proposed to overcome this problem. A prototype circuit has been built which provides dc bias current to the base of the transistors. Experimental results are compared with theoretical calculations to demonstrate the validity of the design. The proposed design decreases the peak and average power losses by about 8 times, when compared to conventional designs.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.151-161
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• 2013

An active power factor correction (PFC) circuit is presented which employs a newly proposed input voltage sensor-less control technique operated in continuous conduction mode (CCM) and critical conduction mode (CRM). The conventional PFC circuit with input voltage sensor-less control technique degrades the power factor (PF) under the light load condition due to DCM operation. In the proposed PFC circuit, the switching frequency is basically 70KHz in CCM operation. In light load condition, however, the PFC circuit operates in CRM and the switching frequency is increased up to 200KHz. So CCM/CRM operation of the PFC circuit alleviates the decreasing of the PF in light load condition. The proposed PFC controller IC has been implemented in a $0.35{\mu}m$ BCDMOS process and a 240W PFC prototype is built. Experimental results shows the PF of the proposed PFC circuit is improved up to 10% from the one employing the conventional CCM/DCM dual mode control technique. Also, the PF is improved up to 4% in the light load condition of the IEC 61000-3-2 Class D specifications.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.5
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• pp.479-488
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• 1991

A novel three-phase quasi-resonant dc link inverter (QRI)with a switch connected between dc voltage source and resonant inductor is proposed. According to the state of switching and load current, the operating mode of the proposed inverter scheme is classified into free-wheeling, inverting, and rectifying mode. By examining the behavior of the circuit in each operating mode, an equivalent circuit which represents all the modes in a unified manner is derived. The operating principle of QRI at inverting mode is analyzed, and it is shown that the maximum voltage of resonant dc link is confined to twice the dc source voltage and that both the zero voltage switching of inverter and the zero current switching of inserted switch are guaranteed. An appropriate current control algorithm is suggested, and the opeating characteristics of proposed resonant inverter are verified through both simulation and experiment.

• ETRI Journal
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• v.31 no.2
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• pp.243-245
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• 2009

A novel ultra-low-power readout circuit for a pH-sensitive ion-sensitive field-effect transistor (ISFET) is proposed. It uses an ISFET/reference FET (REFET) differential pair operating in weak-inversion and a simple current-mode metal-oxide semiconductor FET (MOSFET) translinear circuit. Simulation results verify that the circuit operates with excellent common-mode rejection ability and good linearity for a single pH range from 4 to 10, while only 4 nA is drawn from a single 1 V supply voltage.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.80.1-80
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• 2002

In this article, an alternative analog multiplier circuit, using the translinear second-generation current conveyors with the external resistors. The realization method makes use of the inherited translinear loop of the current conveyor offering the positive-supply current that provides in the quartersquare algebraic identity. The proposed circuit operates in voltage mode and it achieves a high accuracy. The PSPICE simulation results confirm that the performances of the proposed multiplier circuit, such as dynamic range and accuracy, are agreed with the theoretical results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.794-803
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• 1987

In this paper, the SPICE 2.G6 JFET subroutine and other related subroutines are modified for circuit simulation of GaAs MESFET IC's. The hyperbolic tangent model is used for the drain current-voltage characteristics of GaAs MESFET's and derived channel-conductance and drain-conductance model from the above current model are implemented into small-signal model of GaAs MESFET's. And, device capacitance model which consider after-pinch-off state are modified, and device charge model for SPICE 2G.6 are proposed. The result of modification is shown to be suitable for GaAs circuit simulator, showing good agreement with experimetal results. Forthermore the DC convergence of this paper is better than that of SPICE 2.G JFET subroutine. GaAs MESFET model in this paper is applied for both depletion mode GaAs MESFET and enhancement-mode GaAs MESFET without difficulty.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.399-400
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• 2012

The proposed battery charger presented in this paper is suitable for Lead-Acid Battery and the dc/dc buck converter topology is applied as a charger circuit. The technique adopted in this charger is constant current & constant voltage dual mode, which is decided by the value of voltage of proposed battery. Automatic mode change function is detected by the percentage value of level of battery charging. CC Mode (Constant Current Mode) is operated when charging level is below 80% of the total charging of Battery voltage and above 80% of battery voltage charging, CV Mode (Constant Voltage Mode) is automatically operated. As the charging level exceeds 120%, it automatically terminates charging. The feedback signal to the PWM generator for charging the battery is controlled by using the current and voltage measurement circuits simultaneously. This technique will degrade the damage of proposed type of battery and improve the power efficiency of charger. Finally, a prototype charger circuit designed for a 12-V 7-Ah lead acid battery is constructed and tested to confirm the theoretical predictions. Satisfactory performance is obtained from simulation and the experimental results.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.255-259
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• 2008

In this paper, a current-mode integrator for low-voltage, low-power analog integrated circuits is presented. Using the proposed current-mode integrator, the baseband analog filter is designed for WCDMA wireless communication. To verify the proposed current-mode integrator circuit, Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS parameter is performed and achieved 44.9dB gain, 15.7MHz unity gain frequency. The described 3rd-order current-mode baseband analog filter is composed of the proposed current-mode integrator, and SFG(Signal Flow Graph) method is used to realize the baseband filter. The simulated results show 2.12MHz cutoff frequency which is suitable for WCDMA baseband block.