• Progress in Superconductivity and Cryogenics
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• v.16 no.4
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• pp.44-48
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• 2014

A liquid nitrogen-cooled prepolarization ($B_p$) coil made for ultra-low field nuclear magnetic resonance and magnetic resonance imaging (ULF-MR) designed to generate 7 mT/A was fabricated. However, with suspected internal insulation failure, the coil was investigated in order to find out the source of the failure. This paper reports detailed build of the failed $B_p$ coil and a number of analysis methods utilized to figure out the source and the mode of failure. The analysis revealed that pyrolytic graphite sheet linings put on either sides of the coil for better thermal conduction acted as an electrical bridge between inner and outer layers of the coil to short out the coil whenever a moderately high voltage was applied across the coil. A simple model circuit simulation corroborated the analysis and further revealed that the failed insulation acted effectively as a damping resistor of $R_{d,eff}=6{\Omega}$ across the coil. This damping resistance produced a 50 ms-long voltage tail after the coil current was ramped down, making the coil not suitable for use in ULF-MR, which requires complete removal of magnetic field from $B_p$ coil within milliseconds.

• Journal of Electrical Engineering and Technology
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• v.2 no.1
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• pp.89-97
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• 2007

This paper presents a new circuit topology of active edge resonant snubbers assisted half-bridge soft switching PWM inverter type DC-DC high power converter for DC bus feeding power plants. The proposed DC-DC power converter is composed of a typical voltage source-fed half-bridge high frequency PWM inverter with a high frequency planar transformer link in addition to input DC busline side power semiconductor switching devices for PWM control scheme and parallel capacitive lossless snubbers. The operating principle of the new DC-DC converter treated here is described by using switching mode equivalent circuits, together with its unique features. All the active power switches in the half-bridge arms and input DC buslines can achieve ZCS turn-on and ZVS turn-off commutation transitions. The total turn-off switching losses of the power switches can be significantly reduced. As a result, a high switching frequency IGBTs can be actually selected in the frequency range of 60 kHz under the principle of soft switching. The performance evaluations of the experimental setup are illustrated practically. The effectiveness of this new converter topology is proved for such low voltage and large current DC-DC power supplies as DC bus feeding from a practical point of view.

• Journal of IKEEE
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• v.23 no.3
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• pp.1061-1067
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• 2019

In this paper, a highly integrated 3-channel DC-DC converter is designed using power transistor width scaling (PTWS). For positive voltage, $V_{POS}$, a boost converter is designed using the set-time variable pulse width modultaion (SPWM) dual-mode and PTWS to improve efficiency at light load. For negative voltage, $V_{NEG}$, a 0.5 x regulated inverting charge pump is designed with pulse skipping modulation (PSM) controller to reduce power consumption, and for an additional positive voltage, $V_{AVDD}$, a LDO circuit is designed. The proposed DC-DC converter has been designed using a $0.18{\mu}m$ BCDMOS process. Simulation results show that the proposed converter has power efficiency of 56%~90% for load current range of 1 mA~70 mA and output ripple voltage less than 5 mV at positive voltage.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2430-2434
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• 2005

Automatic FPC punching instrument for the improvement of working condition and cost saving is introduced in this paper. FPC(flexible printed circuit) is used to detect the contact position of K/B and button like a cellular phone. Depending on the quality of the printed ink and position of reference punching point to the FPC, the resistance and current are varied to the malfunctioning values. The size of reference punching point is 2mm and the above. Because the punching operation is done manually, the accuracy of the punching degree is varied with operator's condition. Recently, The punching accuracy has deteriorated severely to the 2mm punching reference hall so that assembly of the K/B has hardly done. To improve this manual punching operation to the FPC, automatic FPC punching system is introduced. Precise mechanical parts like a 5-step stepping motor and ball screw mechanism are designed and tested and low cost PC camera is used for the sake of cost down instead of using high quality vision systems for the FA. 3D Mechanical design tool(Pro/E) is used to manage the exact tolerance circumstances and avoid design failures. Simulation is performed to make the complete vision based punching machine before assembly, and this procedure led to the manufacturing cost saving. As the image processing algorithms, dilation, erosion, and threshold calculation is applied to obtain an exact center position from the FPC print marks. These image processing algorithms made the original images having various noises have clean binary pixels which is easy to calculate the center position of print marks. Moment and Least square method are used to calculate the center position of objects. In this development circumstance, Moment method was superior to the Least square one at the calculation of speed and against noise. Main control panel is programmed by Visual C++ and graphical Active X for the whole management of vision based automatic punching machine. Operating modes like manual, calibration, and automatic mode are added to the main control panel for the compensation of bad FPC print conditions and mechanical tolerance occurring in the case of punch and die reassembly. Test algorithms and programs showed good results to the designed automatic punching system and led to the increase of productivity and huge cost down to law material like FPC by avoiding bad quality.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.715-720
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• 2016

This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1235-1242
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• 2008

In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.239-245
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• 2016

In this study, a 12 V PWM boost converter was designed with the optimal values of the external components of the power stage was well as the compensation stage for smart electronic applications powered by a battery device. The 12 V boost PWM converter consisted of several passive elements, such as a resistor, inductor and capacitor with a diode, power MOS switch and control IC chip for the control PWM signal. The devices of the power stage and compensation stage were designed to maintain stable operation under a range of load conditions as well as achieving the highest power efficiency. The results of this study were first verified by a simulation in SPICE from calculations of the values of major external elements comprising the converter. The design was also implemented on the prototype PCBboard using commercial IC LM3481 from Texas Instruments, which has a nominal output voltage of 12 V. The output voltage, ripple voltage, and load regulation with the line regulation were measured using a digital oscilloscope, DMM tester, and DC power supply. By configuring the converter under the same conditions as in the circuit simulation, the experimental results matched the simulation results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.2
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• pp.16-23
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• 2006

This paper presents a novel single-stage high frequency resonant inverter link type DC-DC converter using zero voltage switching with high power-factor. The proposed topology is integrated half-bridge boost rectifier as power factor corrector(PFC) and half-bridge high frequency resonant converter into a single-stage. The input stage of the half-bridge boost rectifier works in discontinuous conduction mode(DCM) with constant duty cycle and variable switching frequency. So that a boost converter makes the line current follow naturally the sinusoidal line voltage waveform. Simulation results have demonstrated the feasibility of the proposed high frequency resonant converter. Characteristics values based on characteristics analysis through circuit analysis is given as basis data in design procedure. Also, experimental results are presented to verify theoretical discussion. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, fluorescent lamp and DC-DC converter etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.