• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.1C
• /
• pp.96-102
• /
• 2002

Current testing(Iddq testing) on monitoring the quiescent power supply current is an efficient and effective method for CMOS bridging faults. The applicability of this technique, however, requires careful examination. Since cardinality of bridging fault is O($n^2$) and current testing requires much longer testing time than voltage testing, it is important to note that a bridging fault is untestable if the two bridged nodes have the same logic values at all times. Such faults should be identified by a good ATPG tool; otherwise, the fault coverage can become skewed. In this paper, we present an object-oriented redundant fault detection scheme for efficient current testing. Experimental results for ISCAS benchmark circuits show that the improved method is more effective than the previous ones.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.5
• /
• pp.431-438
• /
• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• The Journal of the Acoustical Society of Korea
• /
• v.18 no.3
• /
• pp.43-48
• /
• 1999

IDDQ testing is one of current testing methodologies which increases circuit's reliability by means of finding defects which can't be detected by functional testing in CMOS circuits. In this paper, we design a Built-In Current Sensor(BICS) circuit, which can be embedded in chip under test, that performs IDDQ testing. Furthermore, it is designed for IDDQ testing of memories and implemented to carry out testing at high-speed by using small number of transistors.

• Journal of Magnetics
• /
• v.14 no.2
• /
• pp.97-100
• /
• 2009

A new eddy current testing probe was developed to separate the eddy current signal distortion caused by permeability variation clusters and ordinary defects created in steam generator tubes. Signal processing circuits were inserted into the probe to increase the signal-to-noise ratio and allow digital signal transmission. The new probe could measure and separate the magnetic phases created in the steam generator tubes in the operating environment of a nuclear power plant. Furthermore, the new eddy current testing probe can measure the defects in steam generator tubes as rapidly as a bobbin probe with enhanced testing speed and reliability of defect detection.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.22 no.10
• /
• pp.968-973
• /
• 2012

Slam testing is a mandatory testing process to evaluate the fatigue resistance of a door plate module before delivering it to car makers. This process is very hard job to complete it since the testing facilities are considerably expensive and the required testing time is relatively very long, i.e. more than eight days for a single specimen. In this paper, an accelerated testing method of a door plate module is proposed using vibration test equipment instead of the current one by exposing to the critical excitation of a door glass. Under the proposed excitation method, the similar testing result can be evaluated within less than two hours. The suitability of the proposed testing method was demonstrated by comparing failure modes of both the current testing method and the proposed one.

• Journal of the Korean Magnetics Society
• /
• v.24 no.6
• /
• pp.171-178
• /
• 2014

Remote Field Eddy Current Testing (RFECT), one of the ways which is a nondestructive testing using electromagnetic fields, can make up for Magnetic Flux Leakage (MFL) weaknesses and general Eddy Current Testing (ECT) weaknesses which is an occurrence of a huge friction force or disadvantage of detecting defects on the outer wall. So many of institutes and laboratories have studied on RFECT for the past 50 years. But There is a lack of discussion about a study on eddy current and magnetic field distributions in a pipe wall and designing of RFECT exciter coil. In this paper, eddy current and magnetic field distributions in a pipe wall and influence of altering variables are analyzed. Also, the optimal design algorithm about the RFECT Exciter coil are proposed, and influence on defect signals caused by alteration of its shape is analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.10A
• /
• pp.1205-1214
• /
• 2004

For tile physical defects occurring in CMOS circuits which are not handled well by voltage-based testing, current testing is remarkable testing technique. Fault models based on defects must accurately describe the behaviour of the circuit containing the defect. In this paper, An efficient collapsing algorithm for fault models often used in current testing is proposed. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults that have to be considered by fault collapsing and its usefulness in various current based testing models.

• Proceedings of the KIEE Conference
• /
• 2006.07b
• /
• pp.695-696
• /
• 2006

The inrush current of transformer cause saturation effects of recovery voltage for short-circuit power testing. the inrush current depends on the residual flux of the transformer core. when inrush current occurs, it is contains a d.c. component and the high harmonic content of the current are of importance to relay protection of testing circuit. this paper describes of decrease method of inrush current for high power short-circuit testing transformer.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.8
• /
• pp.49-63
• /
• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.12
• /
• pp.2127-2137
• /
• 2016

In this paper, characteristic tests for current transformers with maximum mA secondary current of 250 mA is performed. The purpose of this paper is not only to test the mA current transformers by following the IEEE Draft Standard for Current Transformers with Maximum mA Secondary Current of 250mA, but also to take into consideration certain applications in the use of the mA CTs for billing purposes.