• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• Transactions on Electrical and Electronic Materials
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• 제12권6호
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• pp.262-266
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• 2011

A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.

• 한국전기전자재료학회논문지
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• 제23권9호
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• pp.667-670
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• 2010

In this paper, a high voltage current sensing circuit for boost converter is designed and verified by Cadence SPECTRE simulations. The current mirror pair, power and sensing metal-oxide semiconductor field effect transistors (MOSFETs) with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side lateral-diffused MOS transistor (LDMOST) switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35 ${\mu}m$ BCD process show that current sensing is accurate and the pulse frequency modulation (PFM) boost converter using the proposed current sensing circuit satisfies with the specifications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.14-14
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• 2010

A high voltage current sensing circuit for LED driver IC is designed and verfied by Cadence SPECTRE simulations. The current mirror pair, power and sensing MOSFETs with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side LDMOST switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35um BCD process show that current sensing is accurate with properly frequency compensated opamp.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• Journal of Welding and Joining
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• 제18권1호
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• pp.83-90
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• 2000

It was attempted to improve seam-tracking performance by applying a new arc-sensing algorithm for FCAW(flux-cored arc welding) process in fillet joints. For this study the authors have introduced three different weight factors: $\circled1$ arc currents at the weaving end are more weighted, $\circled2$ arc currents are evenly weighted along the weaving, and $\circled3$ arc currents at the weaving center are more weighted. To evaluate the 3 factors the values of signal-to-noise(S/N) ratio has been measured. The values were obtained for various welding conditions with different gaps in horizontal and vertical fillet joints. The test results showed that the S/N ratio of the 1st case was highest which resulted in the best of seam tracking performance. In addition, the comparison between the seam tracking performance in horizontal fillet joints and that in vertical ones has been done, and the result showed that tracking performance in vertical joints was relatively better than that in horizontal joints.

• Current Optics and Photonics
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• 제6권3호
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• pp.288-296
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• 2022

We propose and experimentally demonstrate a novel photonic compressive sensing (CS) scheme for acquiring sparse radio frequency signals with adjustable compression ratio in this paper. The sparse signal to be measured and a pseudo-random binary sequence are modulated on consecutively connected chirped pulses. The modulated pulses are compressed into short pulses after propagating through a dispersive element. A programmable optical filter based on spatial light modulator is used to realize spectral segmentation and demultiplexing. After spectral segmentation, the compressed pulses are transformed into several sub-pulses and each of them corresponds to a measurement in CS. The major advantage of the proposed scheme lies in its adjustable compression ratio, which enables the system adaptive to the sparse signals with variable sparsity levels and bandwidths. Experimental demonstration and further simulation results are presented to verify the feasibility and potential of the approach.

• 대한전자공학회논문지SD
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• 제44권4호
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• pp.86-90
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• 2007

본 논문에서는 DC-DC 변환기에서 효율적으로 sensing 할 수 있는 센서 scheme을 제안하였다. DC-DC 변환기의 최종 출력전압을 되먹임하여 센서의 입력단에서 전류로 변환되며, 센서에 내장된 기준전류와의 전류비교를 통하여 목표전압에 도달했는지의 여부를 감지한다. 이때의 감지동작은 전류 push-pull 동작을 통해 전류 비교 방식을 수행한다. 센서에 내장된 기준전류도 고정된 기준전압을 변환함으로써 구현된다. 본 scheme의 특징은 전압을 전류로 변환하는 데 있어서의 파라미터가 코어 트랜지스터의 (W/L)의 비로써 결정되므로 비교적 정밀하고 기존의 전압 모드 방식과 비교했을 때, 전력소모 측면이나 칩 사이즈측면에서 효율적으로 구현되는 데에 있다. 본 논문에서는 입력 배터리 공급전압 2.2V${\sim}$3.6V에 대해 5V를 출력하는 DC-DC 변환기에 제안하는 센서를 적용하여 0.35um CMOS 공정으로써 구현하고 그 유용성을 확인하였다.

• 센서학회지
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• 제8권6호
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• pp.434-439
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• 1999

집적형 습도센서를 위해 이중게이트 금속을 증착한 차동형 전계효과 트랜지스터를 제조하고 상대습도에 따른 드레인전류 드리프트특성을 조사하였다. 감지소자와 비감지소자의 전류차를 얻기 위해 두 트랜지스터의 종횡비는 250/50으로 같게 하였다. 제조된 습도감지 전계효과 트랜지스터의 표준화된 드레인전류는 상대습도가 30%에서 90%로 증가함에 따라 0.12에서 0.3으로 증가하였다.