• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.447-448
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• 2005

Recently, organic light emitting diodes(OLEDs) is widely used as one of the information display techniques. We synthesized 2-(2-hydroxyphenyl)benzoxazole($Zn(HPB)_2$). We studied the luminescent properties of OLEDs using $Zn(HPB)_2$. The ionization potential(IP) and the electron affinity(EA) of $Zn(HPB)_2$ investigated using cyclic-voltammetry(C-V). The JP, EA and Eg were 6.5eV, 3.0eV and 3.5eV, respectively. The PL and EL spectra of $Zn(HPB)_2$ were observed at the wavelength of 4S0nm. We used $Zn(HPB)_2$ as an emitting layer and hole blocking layer. At the experiment about hole blocking effect, we inserted $Zn(HPB)_2$ between emitting material layer(EML) and cathode, and hole transport layer(HTL) and emitting material layer(EML). We measured current density-voltage and luminance-voltage characteristics at room temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.360.1-360.1
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• 2014

DSSC (Dye-Sensitized Solar Cell)의 TCO (Transparent Conductive Oxide)와 전해질 사이의 전자 재결합(Back reaction)은 DSSC의 효율을 떨어뜨리는 요소 중 하나이다. 이와 같은 문제점을 해결하기 위하여 Blocking layer로서 $TiO_2$ 가 많이 사용되어지고 있다. 본 실험에서는 $HfO_2$ 를 Blocking layer로 사용하여 전자 재결합으로 인한 효율 저하를 막기 위한 연구를 진행하였다. 기존 $TiO_2$ 대비 $HfO_2$는 큰 에너지 밴드갭을 가지고 있어, TCO와 전해질 사이에 전자 재결합을 줄여주는 역할을 하기 때문에 DSSC의 효율 향상을 확인할 수 있다. 효율 측정은 1sun (100 mW/cm, AM1.5)조건에서 solar simulator를 이용하여 측정 했으며, 전자 재결합 감소는 Dark Current, EIS (Electrochemical Impedance spectroscopy)의 측정을 통하여 확인하였다. $HfO_2$를 이용한 blocking layer를 염료 감응 태양전지에 적용하면, 전자 재결합에 의한 손실을 줄여 성능적 측면에서 개선 가능할 것으로 생각된다.

• Journal of the Korean Vacuum Society
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• v.8 no.3A
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• pp.207-212
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• 1999

Undoped InP epilayers with high purity were grown by using $In/PCl_3/H_2$ chloride vapor phase epitaxy. It was found that the growth of InP homoepitaxial layer is optimized at the growth temperature of $630^{\circ}C$ and at the $PCl_3$ molar fraction of $1.2\times10^{-2}$. The carrier concentration of InP epilayer was less than $10^{14} {cm}^{-3}$ from the low temperature (11K) photoluminescence measurement. Growth behavior of undoped InP current blocking layer on reactive ion-etched (RIE) mesas has been investigated for the realization of 1.55 $\mu \textrm m$buried-heterostructure laser diode (BH LD), using chloride vapor phase epitaxy. On the base of InP homoepitaxy, InP current blocking layers were grown at the growth temperatures ranging from $620^{\circ}C$ to $640^{\circ}C$. Almost planar grown surfaces without edge overgrowth were achieved as the growth temperature increased. It implied that higher temperature enhanced the surface diffusion of the growth species on the {111} B planes and suppressed edge overgrowth.

• Journal of the Semiconductor & Display Technology
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• v.7 no.2
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• pp.49-53
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• 2008

The yellow base polymer light emitting diodes(PLEDs) with double emission and hole blocking layers were prepared to improve the light efficiency. ITO(indium tin oxide) and PEDOT : PSS[poly(3,4-ethylenedioxythiophene) : poly(styrene sulfolnate)] were used as cathode and hole transport materials. The PFO[poly(9,9-dioctylfluorene)] and MEH-PPV[poly(2-methoxy-5(2-ethylhe xoxy)-1,4-phenylenevinyle)] were used as the light emitting host and guest materials, respectively. TPBI[Tpbi1,3,5-tris(N-phenylbenzimidazol-2-yl)benzene] was used as hole blocking layer. To investigate the optimization of device structure, we prepared four kinds of PLED devices with different structures such as single emission layer(PFO : MEH-PPV), two double emission layer(PFO/PFO : MEH-PPV, PFO : MEH-PPV/PFO) and double emission layer with hole blocking layer(PFO/PFO : MEH-PPV/TPBI). The electrical and optical properties of prepared devices were compared. The prepared PLED showed yellow emission color with CIE color coordinates of x = 0.48, y = 0.48 at the applied voltage of 14V. The maximum luminance and current density were found to be about 3920 cd/$m^2$ and 130 mA/$cm^2$ at 14V, respectively for the PLED device with the structure of ITO/PEDOT : PSS/PFO/PFO : MEH-PPV/TPBI/LiF/Al.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.10
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• pp.767-770
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• 2010

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

• Current Optics and Photonics
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• v.4 no.4
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• pp.380-390
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• 2020

In this study, the traditional electron-blocking layer (EBL) in (In,Ga)N/GaN light-emitting diodes is replaced by a circular EBL that is the same size as the n-pad. The three-dimensional (3D) nonlinear Poisson, drift-diffusion, and continuity equations are adopted to simulate current transport in the LED and its characteristics. The results indicate that the local carrier-density distribution obtained for the circular EBL design is more uniform than that for the traditional EBL design. This improves the uniformity of local radiative recombination and local internal quantum efficiency (IQE) at high injection levels, which leads to a higher lumped IQE and lower efficiency droop. With the circular EBL, the lumped IQE is higher in the outer active region and lower in the active region under the n-pad. Since most emissions from the active region under the n-pad are absorbed by the n-pad, obviously, an LED with a circular EBL will have a higher external quantum efficiency (EQE). The results also show that this LED works at lower applied voltages.

• Transactions on Electrical and Electronic Materials
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• v.2 no.1
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• pp.32-38
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• 2001

A new small sized Lateral Trench electrode Insulated Gate Bipolar Transistor(LTEIGBT) was proposed to improve the characteristics of conventional Lateral IGBT (LIGBT) and Lateral Trench gate IGBT (LTIGBT). The entire electrode of LTEIGBT was replace with trench-type electrode. The LTEIGBT was designed so that the width of device was no more than 19 ㎛. The Latch-up current densities of LIGBT, LTIGBT and the proposed LTEIGBT were 120A/㎠, 540A/㎠, and 1230A/㎠, respectively. The enhanced latch-up capability of the LTEIGBT was obtained through holes in the current directly reaching the cathode via the p+ cathode layer underneath n+ cathode layer. The forward blocking voltage of the LTEIGBT is 130V. Conventional LIGBT and LTIGBT of the same size were no more than 60V and 100V, respectively. Because the the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and punch through breakdown of LTEIGBT is occurred, lately.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.546-550
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• 2001

A new Lateral Trench Insulated Gate Bipolar Transistor(LTIGBT) with p$^{+}$ diverter was proposed to improve the characteristics of the conventional LTIGBT. The forward blocking voltage of the proposed LTIGBT with p$^{+}$ diverter was about 140V. That of the conventional LTIGBT of the same size was 105V. Because the p$^{+}$ diverter region of the proposed device was enclosed trench oxide layer, he electric field moved toward trench-oxide layer, and punch through breakdown of LTIGBT with p$^{+}$ diverter was occurred, lately. Therefore, the p$^{+}$ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. The Latch-up current densities of the conventional LTIGBT and proposed LTIGBT were 540A/$\textrm{cm}^2$, and 1453A/$\textrm{cm}^2$, respectively. The enhanced latch-up capability of the proposed LTIGBT was obtained through holes in the current directly reaching the cathode via the p$^{+}$ divert region and p$^{+}$ cathode layer beneath n$^{+}$ cathode layer./ cathode layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.