• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.21-25
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• 2015

Bending fatigue characteristics of Cu films and $8{\mu}m$ width Cu interconnects on flexible substrates were investigated, and fatigue reliability improvement was achieved through Mo-Ti alloy adhesion layer. Tensile bending fatigue reliability of Cu interconnects is 3 times lower than that of Cu films, and even compressive bending fatigue reliability of Cu interconnects is 6 times lower than that of Cu films. From these results, mechanical crack formation could be fatal in Cu interconnects. With Mo-Ti adhesion layer, fatigue reliability of Cu films and interconnects were enhanced due to the increase of adhesion strength and the suppression of slip induced crack initiation.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.12
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• pp.37-42
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• 1999

In this paper, some of main processes for the next generation integrated circuits, such as Cu damascene process using CMP, electron beam lithography, $SiO_2$ CVD and RIE, Ti/Cu-CVD were carried cut and then, two level Cu interconnects were accomplished. In the results of CMP unit processes, a 4,635 ${\AA}$/min of removal rate, a selectivity of Cu : $SiO_2$ of 150:1, a uniformity of 4.0% are obtained under process conditions of a head pressure of 4 PSI, table and head speed of 25rpm, a oscillation distance of 40 mm, and a slurry flow rate of 40 ml/min. Also 0.18 ${\mu}m\;SiO_2$ via-line patterns are fabricated using 1000 ${\mu}C/cm^2$ dose, 6 minute and 30 second development time and 1 minute and 30 second etching time. And finally sub-0.2 ${\mu}$ twolevel metal interconnects using the developed processes were fabricated and the problems of multilevel interconnects are discussed.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.111-115
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• 2014

Effect of dynamic electric fields on dielectric breakdown behavior in Cu damascene interconnects was investigated. Among the DC, unipolar, and bipolar pulse conditions, the longest dielectric lifetime is observed under the bipolar condition because backward Cu ion drift occurs when the direction of electric field is changed by 180 degrees and Cu contamination is prohibited as a results. Under the unipolar pulse condition, the dielectric lifetime increases as pulse frequency increases and it exceed the lifetime under DC condition. It suggests that the intrinsic breakdown of dielectrics significantly affect the dielectric breakdown in addition to Cu contamination. As the unipolar pulse width decreases, dielectric bond breakdown is more difficult to occur.

• Korean Journal of Crystallography
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• v.12 no.4
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• pp.233-238
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• 2001

X-ray microdiffraction which uses x-ray beam focused down to a micron size from synchrotron radiation sources allow precision measurements of local orientation and strain variations in polycrystalline materials. Using x-ray microdiffraction setup at Pohang Light Source, we investigated the tex-ture of Cu interconnects with various widths on Si wafer by collecting Laue images and focused to about 2×3㎛ ² in size. Our results show that 1㎛ wide Cu interconnect had grains in rather ran- dom orientation. On the other hand the 20㎛ wide interconnects showed a 〈111〉fiber texture near the center. The grains were 2∼5㎛ long at the 1㎛ wide interconnect and 6∼8㎛ in size at the 20㎛ wide interconnect.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.370-370
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• 2012

Feature size of Cu interconnects keep shrinking into several tens of nanometer level. For this reason, the Cu interconnects face challenging issues such as increase of electro-migration, line-width dependent electrical resistivity increase, and gap-filling difficulty in high aspect ratio structures. As the thickness of the Cu film decreases below 30 nm, the electrical resistivity is not any more constant, but rather exponential. Research on alloying with other elements have been started to inhibit such escalation in the electrical resistivity. A faint trace of Al added in Cu film by sputtering was reported to contribute to suppression of the increase of the electrical resistivity. From an industrial point of view, we introduced cyclic metal organic chemical vapor deposition (MOCVD) in order to control Al concentration in the Cu film more easily by controlling the delivery time ratio of Cu and Al precursors. The amount of alloying element could be lowered at level of below 1 at%. Process of the alloy formation was applied into gap-filling to evaluate the performance of the gap-filling. Voidless gap-filling even into high aspect ratio trenches was achieved. In-depth analysis will be discussed in detail.

• ETRI Journal
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• v.45 no.5
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• pp.910-921
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• 2023

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.33-36
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• 2003

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.20-25
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• 1998

Cu removal rates for various SiO$_2$ trench pitch sizes and densities and AFM images of surface profiles after global planarization using Cu CMP technology are investigated. In the experimental results, Cu removal rates are increasing as the pattern densities and pattern pitches are getting high and low, respectively, and then decreasing after local planarization. The rms roughness after global planarization are about 120$\AA$. AFM images with a 50% pattern density for 1${\mu}{\textrm}{m}$ and 2${\mu}{\textrm}{m}$ pitches show that thicknesses of 120~330$\AA$ Cu interconnects have been peeled off and oxide erosion of Cu/Sio$_2$ sidewall is observed. However, AFM images with a 50% pattern density for 10${\mu}{\textrm}{m}$ and 15${\mu}{\textrm}{m}$ pitches show that 260~340$\AA$ thick Cu interconnects have been trenched at the boundaries of Cu/Sio$_2$ sidewall.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.53-53
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• 2011

As the dimension of Cu interconnects has continued to reduce, its resistivity is expected to increase at the nanoscale due to increased surface and grain boundary scattering of electrons. To suppress increase of the resistivity in nanoscale interconnects, alloying Cu with other metal elements such as Al, Mn, and Ag is being considered to increase the mean free path of the drifting electrons. The formation of Al alloy with a slight amount of Cu broadly studied in the past. The study of Cu alloy including a very small Al fraction, by contrast, recently began. The formation of Cu-Al alloy is limited in wet chemical bath and was mainly conducted for fundamental studies by sputtering or evaporation system. However, these deposition methods have a limitation in production environment due to poor step coverage in nanoscale Cu metallization. In this work, gap-filling of Cu-Al alloy was conducted by cyclic MOCVD (metal organic chemical vapor deposition), followed by thermal annealing for alloying, which prevented an unwanted chemical reaction between Cu and Al precursors. To achieve filling the Cu-Al alloy into sub-100nm trench without overhang and void formation, furthermore, hydrogen plasma pretreatment of the trench pattern with Ru barrier layer was conducted in order to suppress of Cu nucleation and growth near the entrance area of the nano-scale trench by minimizing adsorption of metal precursors. As a result, superconformal gap-fill of Cu-Al alloy could be achieved successfully in the high aspect ration nanoscale trenches. Examined morphology, microstructure, chemical composition, and electrical properties of superfilled Cu-Al alloy will be discussed in detail.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.53-58
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• 2005

We researched damage formation and failure mechanism under DC(direct current) and AC(alternative current) in order to estimate reliability of Cu interconnects in ULSI. Higher current density and temperature induces more short TTF(time to failure) during interconnects carry DC. Measurement reveals that Cu electromigration has activation energy of 0.96eV and current density exponent value of 4. Thermal fatigue is occurred under DC, and higher frequency and ${\Delta}$T value gives more severe damage during interconnects carry AC Through failure morphology analysis with respect to texture, we observed that damages had grown widely and facetted grains had appeared in (100)grain but damages in (111) had grown thickness direction of line and had induced a failure rapidly.