• Title/Summary/Keyword: Cu defect

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A study on the defect of electroplated Copper/diffusion barrier interface for Cu nano-interconnect (구리 나노배선에서의 전해 구리도금막과 피복층 계면 결함에 관한 연구)

  • Lee, Min-Hyeong;Lee, Hong-Gi;Lee, Ho-Nyeon;Heo, Jin-Yeong
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2011.05a
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    • pp.51-52
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    • 2011
  • 본 연구에서는 전해 구리도금막과 SiN 피복층 사이의 힐락 (Hillock) 및 보이드 (Void) 결함에 미치는 전해 구리도금 공정 및 CVD SiN 피복층 증착 전 NH3 플라즈마 처리 효과에 대해 연구하였다. SiN 피복층 증착전 NH3 플라즈마 효과를 정량화하기 위해 실험계획법을 이용해 NH3 플라즈마 공정 인자가 힐락 결함의 밀도에 미치는 영향에 대해 고찰하였다. 실험결과, 힐락 결함의 밀도는 NH3 플라즈마 인가 시간에 비례한다는 것을 알았다. 보이드 결함의 경우, 구리 씨앗층 및 NH3 플라즈마 조건의 최적화를 통해 구리 씨앗층의 표면 조도를 최소화할 경우 보이드 결함이 최소화된다는 것을 알 수 있었다. 이는 구리 씨앗층의 표면 조도를 최소화함에 따라 전해 구리도금막의 결정립 크기가 커져 결정립 계면에 존재하는 불순물 양이 줄어들었기 때문인 것으로 사료된다.

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Thermal Compression of Copper-to-Copper Direct Bonding by Copper films Electrodeposited at Low Temperature and High Current Density (저온 및 고전류밀도 조건에서 전기도금된 구리 박막 간의 열-압착 직접 접합)

  • Lee, Chae-Rin;Lee, Jin-Hyeon;Park, Gi-Mun;Yu, Bong-Yeong
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2018.06a
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    • pp.102-102
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    • 2018
  • Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

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도핑하지 않은 다이아몬드 박막의 전기전도 경로와 기구

  • 이범주;안병태;백영준
    • Proceedings of the Korean Vacuum Society Conference
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    • 1999.07a
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    • pp.60-60
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    • 1999
  • 단결정 다이아몬드의 열전도도는 약 22W/cm.K로 열전도도가 가장 큰 물질로 알려져 있으며, 비저항은 10$\Omega$.cm 이상의 높은 값을 갖는다. 대부분 열전도도가 큰 것으로 알려진 물질들은 Cu, Ag 등과 같이 전자의 흐름에 의하여 열이 전도되기 때문에 큰 전기전도도를 함께 갖는 것일 일반적이다, 그러나, 다이아몬드는 빠른 phonon의 이동에 의하여 열전도가 이루어지므로 전기적으로 절연 특성을 갖으면서도 큰 열전도가 가능하다. 단결정 다이아몬드는 고방열 절연체로서 이상적인 물질 특성을 보여준다. 전기절연성을 갖는 열전도층으로 다이아몬드를 이용하기 위해서는 저가로 제조가 용이한 화학기상증착법을 이용하여야 한다. 화학기상증착법으로 제조된 다결정 다이아몬드 박막의 열전도도는 약 21W/cm.K로 여전히 매우 높은 값을 갖는 것으로 알려져 있지만, 비저항 값은 인위적으로 도핑을 전혀 하지 않은 상태에서도 106$\Omega$.cm 정도의 낮은 값을 갖는다. 전혀 도핑을 하지 않았음에도 전도성을 갖는 특이한 특성을 다결정 다이아몬드가 보여 주고 있으므로 이에 대한 연구는 주로 전기 전도성을 갖는 특이한 특성을 다결정 다이아몬드가 보여주고 있으므로 이에 대한 연구는 주로 전기전도성의 원인을 규명하는데 집중되고 있다. 아직 명확한 전도 기구는 제안되고 있지 못하지만 전도성의 원인은 수소와 관련이 있고 전도는 표면을 통하여 이루어진다는 것이다. 산(acid)을 이용하여 다결정 다이아몬드 박막을 세척하면 전기 전도성이 사라지고 높은 저항값을 갖는 박막을 얻게 되는데 박막을 세척하는 공정은 박막의 표면만을 변호시키므로 표면에 있던 전기전도층이 용액 처리를 통하여 제거되므로 전도성이 사라진다고 생각하는 것이다. 그러나, 본 연구에서는 두께가 두꺼울수록 저항값이 증가하는 것이 관찰되었고 기존의 측정방식인 수평적인 저항 측정법에 대하여 수직적 방향으로 저항을 측정하면 저항값이 1/2 정도 작게 측정되었다. 다결정 다이아몬드에서 표면을 통하여 전류가 흐른다면 박막의 두께에 따른 변화가 나타나지 않아야 하고 수직적인 전류 측정법이 오히려 더 큰 저항을 보여주어야 한다. 기존의 표면 전도 모델로는 설명되지 못하는 현상들이 관찰되었고 정확한 전기 전도 경로를 확인하기 위하여 전해 도금법으로 금속들이 석출되는 모습을 관찰하였다. 이 방법을 통하여 다결정 다이아몬드에서 전류는 결정입계를 통하여 전도됨을 알 수 있었다. 온도에 따른 다결정 다이아몬드의 전기전도도 변화를 관찰하였고 이로부터 활성화 에너지 값을 구할 수 있었다. 다결정 다이아몬드의 전도도는 온도에 따라서 0.049eV와 0.979eV의 두 개의 활성화 에너지를 갖는 구간으로 나뉘어졌다. 이로부터 다결정 다이아몬드에는 활성화 에너지 값이 다른 두 종류의 defect level이 형성되는 것으로 추정할 수 있고 이 낮은 defect level에 의하여 전도성을 갖는 것으로 생각된다.

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High Resolution TEM Observations in $Hg_{1-x}\;Tl_{x}\;Ba_{2}(Ca_{0.86}\;Sr_{0.14})_{2}\;Cu_{3}\;O_{8+\delta}$ Superconductors (고온 초전도체 $Hg_{1-x}\;Tl_{x}\;Ba_{2}(Ca_{0.86}\;Sr_{0.14})_{2}\;Cu_{3}\;O_{8+\delta}$의 고분해능 TEM에 의한 구조 관찰)

  • Lee, Hwack-Joo;Ryu, Hyun;Hur, Nam-H.;Park, Yong-K.
    • Applied Microscopy
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    • v.25 no.4
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    • pp.124-131
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    • 1995
  • High resolution transmission electron microscopic observations on the $Hg_{1-x}\;Tl_{x}\;Ba_{2}(Ca_{0.86}\;Sr_{0.14})_{2}\;Cu_{3}\;O_{8+\delta}$(x=0.00, 0.25, 0.50, 0.75) were carried out using side-entry type TEM working at 300 kV. The TEM samples are prepared by powder method. The pellets are crushed in agatar motar and suspended in $CCl_4$, solution and scooped in holely carbon microgrid. The 1223 structures are observed in all samples with [010] zone axis. Except x=0.25 sample, the lattice parameter a and c tend to decrease as the thallium contents are increased ranging from 0.3936 nm to 0.3713 nm for a, and from 1.6131 nm to 1.5138 nm for c parameter. Those of x=0.25 sample are reduced too much, 0.3785 nm for a, 1.5375 nm for c. The sample with x=0.25 shows the intergrowth of 1223 and 1234 structure with the ratio of 19 to 1. As the thallium content increases, the structures become more stable without having any defect. The samples are damaged by electron beam irradiation during the observation, however the structure can endure longer as the thallium contents are increased.

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Secondary Phase and Defects in Cu2ZnSnSe4 Solar Cells with Decreasing Absorber Layer Thickness

  • Kim, Young-Ill;Son, Dae-Ho;Lee, Jaebaek;Sung, Shi-Joon;Kang, Jin-Kyu;Kim, Dae-Hwan;Yang, Kee-Jeong
    • Current Photovoltaic Research
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    • v.9 no.3
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    • pp.84-95
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    • 2021
  • The power conversion efficiency of Cu2ZnSnSe4 (CZTSe) solar cells depends on the absorber layer thickness; however, changes in the characteristics of the cells with varying absorber layer thickness are unclear. In this study, we investigated the changes in the characteristics of CZTSe solar cells for varying absorber layer thickness. Five absorber thicknesses were employed: CZTSe1 2.78 ㎛, CZTSe2 1.01 ㎛, CZTSe3 0.55 ㎛, CZTSe4 0.29 ㎛, and CZTSe5 0.15-0.23 ㎛. The efficiency of the CZTSe solar cells decreased as the absorber thickness decreased, resulting in power conversion efficiencies of 10.45% (CZTSe1), 8.67% (CZTSe2), 7.14% (CZTSe3), 3.44% (CZTSe4), and 1.54% (CZTSe5). As the thickness of the CZTSe absorber layer decreased, the electron-hole recombination at the grain boundaries and the absorber-back-contact interface increased. This caused an increase in the current loss, owing to light loss in the long-wavelength region. In addition, as the thickness of the CZTSe absorber layer decreased, more ZnSe was produced, and the resulting defects and defect clusters led to an open-circuit voltage loss.

A Study on the Magnetic Properties of Ceramics Superconductors for Simpllified Testing System (간소화 시스템적용을 위한 자기특성)

  • Lee, Sang-Heon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.2
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    • pp.339-341
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    • 2012
  • The high Tc superconductor of YBCO system with the nominal composition of precursor was prepared from mixed powders of $Y_2O_3$, $BaCO_3$, CuO and $TiO_2$ by the thermal pyrolysis method. The effect of $TiO_2$ doping to Y based ceramics superconductors fabricated by the thermal pyrolysis reaction, to investigate the effect of the dopant on the superconductivity. The voltage appearing across the field-cooled HTS sample increased with external magnetic field. The improvement of critical current property as well as the mechanical property is important for the application. The improvement of the critical current can be achieved by forming the nano size defect working as a flux pining center inside the superconductor. We simply added $TiO_2$ to starting materials to dope $TiO_2$ and observed an increase in the trapped field and the critical current density up to at least 5 wt % $TiO_2$. The $TiO_2$ was converted to fine $BaTiO_3$ particles which were trapped in YBCO matrix during the sintering process. We observed a peak effect of Jc that can be attributed to $TiO_2$ doping and results suggest that introducing a proper amount of pinning centers can significantly enhance current density.

Room Temperature Preparation of Electrolytic Silicon Thin Film as an Anode in Rechargeable Lithium Battery (실리콘 상온 전해 도금 박막 제조 및 전기화학적 특성 평가)

  • Kim, Eun-Ji;Shin, Heon-Cheol
    • Korean Journal of Materials Research
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    • v.22 no.1
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    • pp.8-15
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    • 2012
  • Silicon-based thin film was prepared at room temperature by an electrochemical deposition method and a feasibility study was conducted for its use as an anode material in a rechargeable lithium battery. The growth of the electrodeposits was mainly concentrated on the surface defects of the Cu substrate while that growth was trivial on the defect-free surface region. Intentional formation of random defects on the substrate by chemical etching led to uniform formation of deposits throughout the surface. The morphology of the electrodeposits reflected first the roughened surface of the substrate, but it became flattened as the deposition time increased, due primarily to the concentration of reduction current on the convex region of the deposits. The electrodeposits proved to be amorphous and to contain chlorine and carbon, together with silicon, indicating that the electrolyte is captured in the deposits during the fabrication process. The silicon in the deposits readily reacted with lithium, but thick deposits resulted in significant reaction overvoltage. The charge efficiency of oxidation (lithiation) to reduction (delithiation) was higher in the relatively thick deposit. This abnormal behavior needs to clarified in view of the thickness dependence of the internal residual stress and the relaxation tendency of the reaction-induced stress due to the porous structure of the deposits and the deposit components other than silicon.

Manufacturing Techniques of Bronze Medium Mortars(Jungwangu, 中碗口) in Joseon Dynasty (조선시대 중완구의 제작 기술)

  • Huh, Ilkwon;Kim, Haesol
    • Conservation Science in Museum
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    • v.26
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    • pp.161-182
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    • 2021
  • A jungwangu, a type of medium-sized mortar, is a firearm with a barrel and a bowl-shaped projectileloading component. A bigyeokjincheonroe (bombshell) or a danseok (stone ball) could be used as a projectile. According to the Hwaposik eonhae (Korean Translation of the Method of Production and Use of Artillery, 1635) by Yi Seo, mortars were classified into four types according to its size: large, medium, small, or extra-small. A total of three mortars from the Joseon period have survived, including one large mortar (Treasure No. 857) and two medium versions (Treasure Nos. 858 and 859). In this study, the production method for medium mortars was investigated based on scientific analysis of the two extant medium mortars, respectively housed in the Jinju National Museum (Treasure No. 858) and the Korea Naval Academy Museum (Treasure No. 859). Since only two medium mortars remain in Korea, detailed specifications were compared between them based on precise 3D scanning information of the items, and the measurements were compared with the figures in relevant records from the period. According to the investigation, the two mortars showed only a minute difference in overall size but their weight differed by 5,507 grams. In particular, the location of the wick hole and the length of the handle were distinct. The extant medium mortars are highly similar to the specifications listed in the Hwaposik eonhae. The composition of the medium mortars was analyzed and compared with other bronze gunpowder weapons. The surface composition analysis showed that the medium mortars were made of a ternary alloy of Cu-Sn-Pb with average respective proportions of (wt%) 85.24, 10.16, and 2.98. The material composition of the medium mortars was very similar to the average composition of the small gun from the Joseon period analyzed in previous research. It also showed a similarity with that of bronze gun-metal from medieval Europe. The casting technique was investigated based on a casting defect on the surface and the CT image. Judging by the mold line on the side, it appears that they were made in a piece-mold wherein the mold was halved and using a vertical design with molten metal poured through the end of the chamber and the muzzle was at the bottom. Chaplets, an auxiliary device that fixed the mold and the core to the barrel wall, were identified, which may have been applied to maintain the uniformity of the barrel wall. While the two medium mortars (Treasure Nos. 858 and 859) are highly similar to each other in appearance, considering the difference in the arrangement of the chaplets between the two items it is likely that a different mold design was used for each item.

Study of ZnS/CIGS Hetero-interface for Cd-free CIGS Solar Cells (Cd-free 태양전지를 위한 ZnS/CIGS 이종접합 특성 향상 연구)

  • Shin, Donghyeop;Kim, Jihye;Go, Youngmin;Yun, Jaeho;Ahn, Byungtae
    • 한국신재생에너지학회:학술대회논문집
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    • 2011.05a
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    • pp.106.1-106.1
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    • 2011
  • The Cu(In,Ga)Se2 (CIGS) thin film solar cells have been achieved until almost 20% efficiency by NREL. These solar cells include chemically deposited CdS as buffer layer between CIGS absorber layer and ZnO window layer. Although CIGS solar cells with CdS buffer layer show excellent performance, the short wavelength response of CIGS solar cell is limited by narrow CdS band gap of about 2.42 eV. Taking into consideration the environmental aspect, the toxic Cd element should be replaced by a different material. Among Cd-free candidate materials, the CIGS thin film solar cells with ZnS buffer layer seem to be promising with 17.2%(module by showa shell K.K.), 18.6%(small area by NREL). However, ZnS/CIGS solar cells still show lower performance than CdS/CIGS solar cells. There are several reported reasons to reduce the efficiency of ZnS/CIGS solar cells. Nakada reported ZnS thin film had many defects such as stacking faults, pin-holes, so that crytallinity of ZnS thin film is poor, compared to CdS thin film. Additionally, it was known that the hetero-interface between ZnS and CIGS layer made unfavorable band alignment. The unfavorable band alignment hinders electron transport at the heteo-interface. In this study, we focused on growing defect-free ZnS thin film and for favorable band alignment of ZnS/CIGS, bandgap of ZnS and CIGS, valece band structure of ZnS/CIGS were modified. Finally, we verified the photovoltaic properties of ZnS/CIGS solar cells.

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Simple and Clean Transfer Method for Intrinsic Property of Graphene

  • Choe, Sun-Hyeong;Lee, Jae-Hyeon;;Kim, Byeong-Seong;Choe, Yun-Jeong;Hwang, Jong-Seung;Hwang, Seong-U;Hwang, Dong-Mok
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.659-659
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    • 2013
  • Recently, graphene has been intensively studied due to the fascinating physical, chemical and electrical properties. It shows high carrier mobility, high current density, and high thermal conductivity compare with conventional semiconductor materials even it has single atomic thickness. Especially, since graphene has fantastic electrical properties many researchers are believed that graphene will be replacing Si based technology. In order to realize it, we need to prepare the large and uniform graphene. Chemical vapor deposition (CVD) method is the most promising technique for synthesizing large and uniform graphene. Unfortunately, CVD method requires transfer process from metal catalyst. In transfer process, supporting polymer film (Such as poly (methyl methacrylate)) is widely used for protecting graphene. After transfer process, polymer layer is removed by organic solvents. However, it is impossible to remove it completely. These organic residues on graphene surface induce quality degradation of graphene since it disturbs movement of electrons. Thus, in order to get an intrinsic property of graphene completely remove of the organic residues is the most important. Here, we introduce modified wet graphene transfer method without PMMA. First of all, we grow the graphene from Cu foil using CVD method. And then, we deposited several metal films on graphene for transfer layer instead of PMMA. Finally, we fabricate graphene FET devices. Our approaches show low defect density and non-organic residues in comparison with PMMA coated graphene through Raman spectroscopy, SEM and AFM. In addition, clean graphene FET shows intrinsic electrical characteristic and high carrier mobility.

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