• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.81-88
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• 2019

In this study, the effects of graphene oxide (GO) addition on electromigration (EM) lifetime of Sn-3.0Ag-0.5Cu Pb-free solder joint between a ball grid array (BGA) package and printed circuit board (PCB) were investigated. After as-bonded, $(Cu,Ni)_6Sn_5$ intermetallic compound (IMC) was formed at the interface of package side finished with electroplated Ni/Au, while $Cu_6Sn_5$ IMC was formed at the interface of OSP-treated PCB side. Mean time to failure of solder joint without GO solder joint under $130^{\circ}C$ with a current density of $1.0{\times}10^3A/cm^2$ was 189.9 hrs and that with GO was 367.1 hrs. EM open failure was occurred at the interface of PCB side with smaller pad diameter than that of package side due to Cu consumption by electrons flow. Meanwhile, we observed that the added GO was distributed at the interface between $Cu_6Sn_5$ IMC and solder. Therefore, we assumed that EM reliability of solder joint with GO was superior to that of without GO by suppressing the Cu diffusion at current crowding regions.

• Current Photovoltaic Research
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• v.10 no.2
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• pp.39-48
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• 2022

A Se-containing Cu/SnSe₂/ZnSe precursor was employed to introduce S to the precursor to form Cu₂ZnSn(S,Se)₄ (CZTSSe) film. The morphology of CZTSSe films strongly varied with two different pre-annealing environments: S and N₂. The CZTSSe film with S pre-annealing showed a dense morphology with a smooth surface, while that with N₂ pre-annealing showed a porous film with a plate-shaped grains on the surface. CuS and Cu₂Sn(S,Se)₃ phases formed during the S pre-annealing stage, while SnSe and Cu₂SnSe₃ phases formed during the N₂ pre-annealing stage. The SnSe phase formed during N₂ pre-annealing generated SnS₂ phase that had plate shape and severely aggravated the morphology of CZTSSe film. The power conversion efficiency of the CZTSSe solar cell with S pre-annealing was low (1.9%) due to existence of Zn(S.Se) layer between CZTSSe and Mo substrate. The results indicated that S pre-annealing of the precursor was a promising method to achieve a good morphology for large area application.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.29-35
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• 2003

The Sn-based lead-free solders with varying microstructure were prepared by changing the cooling rate from the melt. Bulky as-cast SnAg, SnAgCu, and SnCu, alloys were cold rolled and thermally stabilized before the creep tests so that there would be very small amount of microstructural change during creep (TS), and thin specimens were water quenched from the melt (WQ) to simulate microstructures of the as-reflowed solders in flip chips. Cooling rates of the WQ specimens were 140∼150 K/sec, and the resultant $\beta-Sn$ globule size was 5∼10 times smaller than that of the TS specimens. Subsequent creep tests showed that the minimum strain rate of TS specimens was about $10_2$ times higher than that of the WQ specimens. Fractographic analyses showed that creep rupture of the TS-SnAgCu specimens occurred by the nucleation of voids on the $Ag_3Sn$ Sn or $Cu_6Sn_5$ particles in the matrix, their subsequent growth by the power-law creep, and inter-linkage of microcracks to form macrocracks which led to the fast failure. On the other hand, no creep voids were found in the WQ specimens due to the mode III shear rupture coming from the thin specimens geometry.

• 연구논문집
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• s.24
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• pp.63-79
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• 1994

This article reports a experimental study of the method to achieve a bond joint at lower temperature in a short time. DC magnetron sputtering of Sn, Sn/Pb, Sn/In and Sn/Cu on copper substrate was provided as an interlayer for Cu to Cu bonding under the air environment. Various examination was conducted and investigated on the effect of experimental parameters such as coating materials, coating time(or coating thickness), bonding temperature and bonding time etc. Bonding was performed at the temperature of $210^\circC-320^\circC$ for 0sec and interfacial reaction between the coated layer and copper substrate was examined using optical, scanning electron microscope and x-ray diffractometer. From the obtained results, it was found that intermetallic compounds layer consisted of $\eta-phase(Cu_6Sn_5)$ and $\beta-phase(Cu_3Sn)$ was formed at the joint interface for almost all coating materials. But the dominant phase formed in the preetched Cu substrate coated with Sn was $\beta-phase$. A characteristic morphology looks like a reaction ring, which was believed as the strong interconnecting regions between two substrates, was found to be formed on the reaction surface of copper substrates. The morphologies and compositions of the intermetallics, which depends on the regions of the reaction surface, was appeared as greatly different. Based on above results, the new bonding process to make the joint at lower temperature for short time can be admitted as a feasible process.

• Journal of Electrochemical Science and Technology
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• v.11 no.1
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• pp.92-98
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• 2020

SnO₂-based high-capacity anode materials are attractive candidate for the next-generation high-performance lithium-ion batteries since the theoretical capacity of SnO₂ can be ideally extended from 781 to 1494 mAh g^-1. Here 3D etched Cu foam is applied as a current collector for electron path and simultaneously a substrate for the SnO₂ coating, for developing an integrated electrode structure. We fabricate the 3D etched Cu foam through an auto-catalytic electroless plating method, and then coat the SnO₂ onto the self-supporting substrate through a simple sol-gel method. The catalytic dissolution of Cu metal makes secondary pores of both several micrometers and several tens of micrometers at the surface of Cu foam strut, besides main channel-like interconnected pores. Especially, the additional surface pores on etched Cu foam are intended for penetrating the individual strut of Cu foam, and thereby increasing the surface area for SnO₂ coating by using even the internal of Cu foam. The increased areal capacity with high structural integrity upon cycling is demonstrated in the SnO₂-coated 3D etched Cu foam. This study not only prepares the etched Cu foam using the spontaneous chemical reactions but also demonstrates the potential for electroless plating method about surface modification on various metal substrates.

• Current Photovoltaic Research
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• v.1 no.2
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• pp.82-89
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• 2013

$Cu_2ZnSnS_4$ thin film have been fabricated by rapid thermal annealing of dc-sputtered metal precursor with Cu/ZnSn/Cu stack in sulfur ambient. A CZTS film with a good uniformity was formed at $560^{\circ}C$ in 6 min. $Cu_2SnS_3$ and $Cu_3SnS_4$ secondary phases were present at $540^{\circ}C$ and a trace amount of $Cu_2SnS_3$ secondary phase was present at $560^{\circ}C$. Single-phase large-grained CZTS film with rough surface was formed at $560^{\circ}C$. Solar cell with best efficiency of 4.7% ($V_{oc}=632mV$, $j_{sc}=15.8mA/cm^2$, FF = 47.13%) for an area of $0.44cm^2$ was obtained for the CZTS absorber grown at $560^{\circ}C$ for 6 min. The existence of second phase at lower-temperature annealing and rough surface at higher-temperature annealing caused the degradation of cell performance. Also poor back contact by void formation deteriorated cell performance. The fill factor was below 0.5; it should be increased by minimizing voids at the CZTS/Mo interface. Our results suggest that CZTS absorbers can be grown by rapid thermal annealing of metallic precursors in sulfur ambient for short process times ranging in minutes.

• Journal of Korea Foundry Society
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• v.20 no.2
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• pp.116-121
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• 2000

Interfacial reaction and mechanical properties between Sn-Zn-X ternary alloys(X : 3wt.%In, 4wt.%Bi) and Cu-substrate were studied. Cu/solder joints were subjected to aging treatments for up to 50days to see interfacial reaction at $100^{\circ}C$ and then were examined changes of microstructure and interfacial compound by optical microscopy, SEM and EDS. Cu/solder joints were aged to 30days and then loaded to failure at cross head speed of 0.3 mm $min^{-1}$ to measure tensile strength. According to the results of the solderability test, additions of In and Bi in the Sn-9wt.%Zn solder improve the wetting characteristics of the alloy and lower the melting temperature. Through the EDS and XRD analysis of Cu/Sn-9wt.%Zn solder joint, it was concluded that the intermetallic compound was the ${\gamma}-Cu_5Zn_8$ phase. Cu-Zn intermetallics at Cu/solder interfaces played an important role in both the microstructure evolution and failure of solder joints. Cu/solder joint strength was decreased by aging treatment, and those phenomenon was closely related to the thickening of intermetallic layer at Cu/solder joints.

• Journal of Welding and Joining
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• v.31 no.3
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• pp.17-21
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• 2013

Sn whiskers are one of the serious causes of the failure of electronics. Sn whiskers grow spontaneously from Sn-based, lead-free finished surfaces, even at room temperature. A primary factor of these Sn whiskers growth is compressive stress, which enhances the diffusion of Sn or other elements. The sources of compressive stress are the growth of non-uniform large intermetallic compounds along the interface between the Sn grain boundary and Cu substrate. Recent studies revealed the methods for reducing Sn whisker growth. This paper gives an overview about recent researches for mitigation methods of Sn whisker growth during nearly room temperature storage.

• Journal of the Korean institute of surface engineering
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• v.35 no.1
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• pp.11-16
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• 2002

As environmental concerns increasing, the electronics industry is focusing more attention on lead free solder alternatives. In this research, we have researched wettability of intermediate solder of Sn3Ag9Bi5In, which include In and Bi and has similar melting temperature to Sn37Pb eutectic solder. We investigated the wetting property of Sn3Ag9Bi5In. To estimate wettability of Sn3Ag9Bi5In solder on various substrates, the wettability of Sn3Ag9Bi5In solder on high-pure Cu-coupon was measured. Cu-coupon that plated Sn, Ni and Au/Ni and Si-wafer adsorbed Ni/Cu under bump metallurgy on one side. As a result, the wetting property of Sn3Ag9Bi5In solder is a little better than that of Sn37Pb and Sn3.5Ag.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.