• The Journal of Society for e-Business Studies
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• v.11 no.2
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• pp.1-11
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• 2006

This paper proposes an efficient inversion algorithm for Galois field GF(2n) by using a modified multi-bit shifting method based on the Montgomery algorithm. It is well known that the efficiency of arithmetic algorithms depends on the basis and many foregoing papers use either polynomial or optimal normal basis. An inversion algorithm, which modifies a multi-bit shifting based on the Montgomery algorithm, is studied. Trinomials and AOPs (all-one polynomials) are tested to calculate the inverse. It is shown that the suggested inversion algorithm reduces the computation time up to 26 % of the forgoing multi-bit shifting algorithm. The modified algorithm can be applied in various applications and is easy to implement.

• Journal of Advanced Navigation Technology
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• v.15 no.5
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• pp.781-788
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• 2011

A sphere-packing problem is to find an arrangement of the spheres to fill as large area of the given space as possible, and covering problems are optimization problems which are dual problems to the packing problems. We generalize the concepts of the weight and the Hamming distance for a binary code to those of Boolean algebra. In this paper, we define a weight and a distance on a Boolean algebra and research some properties of the weight and the distance. Also, we prove the notions of the sphere-packing bound and the Gilbert-Varshamov bound on Boolean algebra.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.1
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• pp.414-430
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• 2016

Verifier-local revocation (VLR) seems to be the most flexible revocation approaches for any group signature scheme, because it just only requires the verifiers to possess some up-to-date revocation information, but not the signers. Langlois et al. (PKC 2014) proposed the first VLR group signature based on lattice assumptions in the random oracle model. Their scheme has at least Õ(n²) ⋅ log N bit group public key and Õ(n) ⋅ log N bit signature, respectively. Here, n is the security parameter and N is the maximum number of group members. In this paper, we present a simpler lattice-based VLR group signature, which is more efficient by a O(log N) factor in both the group public key and the signature size. The security of our VLR group signature can be reduced to the hardness of learning with errors (LWE) and small integer solution (SIS) in the random oracle model.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.1
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• pp.255-262
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• 2011

The advancement of information and communication technology has caused a few dysfunction such as hacking. To keep an organization from a harmful hacking, demands for cryptographic modules have been increased. However, the evaluation criteria of cryptographic modules in Korea have been less firmly established. It is difficult for the consumers of cryptographic module to choose an appropriate cryptographic module, and to establish interoperability between applications and cryptographic modules. This study analyzes evaluation criteria, evaluation processes and evaluation policy of CMVP(Cryptographic Module Verification Program) in the advanced countries. The paper suggests a policy for Korea CMVP, in resulting a provision of foundations for international standard and cooperations for international cryptographic policies and systems.

• Journal of Information Technology Applications and Management
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• v.18 no.3
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• pp.61-72
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• 2011

Trust for the data created, processed and transferred on e-Science environments can be estimated with provenance. The information to form provenance, which says how the data was created and reached its current state, increases as data evolves. It is a heavy burden to trace and verify the massive provenance in order to trust data. On the other hand, it is another issue how to trust the verification of data with provenance. This paper proposes a fast and exact verification of inter-domain data transfer and data origin for e-Science environment based on PKI. The verification, which is called two-way verification, cuts down the tracking overhead of the data along the causality presented on Open Provenance Model with the domain specialty of e-Science environment supported by Grid Security Infrastructure (GSI). The proposed scheme is easy-applicable without an extra infrastructure, scalable irrespective of the number of provenance records, transparent and secure with cryptography as well as low-overhead.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.9
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• pp.4527-4547
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• 2018

Signcryption is a cryptographic primitive that provides authentication (signing) and confidentiality (encrypting) simultaneously at a lower computational cost and communication overhead. With the proposition of certificateless public key cryptography (CLPKC), certificateless signcryption (CLSC) scheme has gradually become a research hotspot and attracted extensive attentions. However, many of previous CLSC schemes are constructed based on time-consuming pairing operation, which is impractical for mobile devices with limited computation ability and battery capacity. Although researchers have proposed pairing-free CLSC schemes to solve the issue of efficiency, many of them are in fact still insecure. Therefore, the challenging problem is to keep the balance between efficiency and security in CLSC schemes. In this paper, several existing CLSC schemes are cryptanalyzed and a new CLSC scheme without pairing based on elliptic curve cryptosystem (ECC) is presented. The proposed CLSC scheme is provably secure against indistinguishability under adaptive chosen-ciphertext attack (IND-CCA2) and existential unforgeability under adaptive chosen-message attack (EUF-CMA) resting on Gap Diffie-Hellman (GDH) assumption and discrete logarithm problem in the random oracle model. Furthermore, the proposed scheme resists the ephemeral secret leakage (ESL) attack, public key replacement (PKR) attack, malicious but passive KGC (MPK) attack, and presents efficient computational overhead compared with the existing related CLSC schemes.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• Journal of IKEEE
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• v.18 no.2
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• pp.198-205
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• 2014

As the development of information technology, the interests in tiny applications such as wearable devices, portable devices and RFID are increased and the importance of low-area encryption circuit is emphasized. This paper proposes a compact architecture of AES-based encryption circuit suitable for tiny applications. The circuit area is reduced by minimizing storage space and sharing computation resources. The synthesized gate-level circuit using 65nm standard cell library consists of 2,241 gates and two $8{\times}16$-bit SRAMs. It can process data at a rate of 50.57Mbits per second. Therefore, the proposed encryption circuit is suitable for various applications requiring very small encryption circuit.

• Journal of Information Processing Systems
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• v.8 no.1
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• pp.159-174
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• 2012

This paper presents a study on a high-performance design for a block cipher algorithm implemented on modern many-core graphics processing units (GPUs). The recent emergence of VLSI technology makes it feasible to fabricate multiple processing cores on a single chip and enables general-purpose computation on a GPU (GPGPU). The GPU strategy offers significant performance improvements for all-purpose computation and can be used to support a broad variety of applications, including cryptography. We have proposed an efficient implementation of the encryption/decryption operations of a block cipher algorithm, SEED, on off-the-shelf NVIDIA many-core graphics processors. In a thorough experiment, we achieved high performance that is capable of supporting a high network speed of up to 9.5 Gbps on an NVIDIA GTX285 system (which has 240 processing cores). Our implementation provides up to 4.75 times higher performance in terms of encoding and decoding throughput as compared to the Intel 8-core system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.578-580
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• 2017

IoT technology poses a lot of security threats. Various algorithms are thus employed in ensuring security of transactions between IoT devices. Advanced Encryption Standard (AES) has gained huge popularity among many other symmetric key algorithms due to its robustness till date. This paper presents a hardware based implementation of the AES algorithm. We present a four-stage pipelined architecture of the encryption and key generation. This method allowed a total plain text size of 512 bits to be encrypted in 46 cycles. The proposed hardware design achieved a maximum frequency of 1.18GHz yielding a throughput of 13Gbps and 800MHz yielding a throughput of 8.9Gbps on the 65nm and 180nm processes respectively.